Dear Eric Nelson,
ensure that transmit and receive buffers are cache-line aligned invalidate cache for each packet as received update receive buffer descriptors one cache line at a time flush cache before transmitting
Original patch by Marek: http://lists.denx.de/pipermail/u-boot/2012-February/117695.html
Signed-off-by: Eric Nelson eric.nelson@boundarydevices.com
V2 addresses some concerns from the ML:
- Use readl()/writel() instead of mapped data structure accesses
- Wrong comment style
- &rbd_base[0] == rbd_base
removed 'volatile' from fec_send().
V3 updates from ML (and Marek): consolidated CONFIG_FEC_DATA_ALIGNMENT and CONFIG_FEC_DESC_ALIGNMENT added cache flushes after initialization of TBD/RBD
drivers/net/fec_mxc.c | 265 +++++++++++++++++++++++++++++++++++-------------- drivers/net/fec_mxc.h | 19 +---- 2 files changed, 189 insertions(+), 95 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1fdd071..94a3927 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -50,6 +50,24 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_FEC_MXC_SWAP_PACKET #endif
+#if ARCH_DMA_MINALIGN > CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_FEC_ALIGN ARCH_DMA_MINALIGN +#else +#define CONFIG_FEC_ALIGN CONFIG_SYS_CACHELINE_SIZE +#endif
Check PPC and let's go with ARCH_DMA_MINALIGN
+#define RXDESC_PER_CACHELINE (CONFIG_FEC_ALIGN/sizeof(struct fec_bd))
+/* Check various alignment issues at compile time */ +#if ((CONFIG_FEC_ALIGN < 16) || (CONFIG_FEC_ALIGN % 16 != 0)) +#error "CONFIG_FEC_ALIGN must be multiple of 16!" +#endif
+#if ((PKTALIGN < CONFIG_FEC_ALIGN) || \
- (PKTALIGN % CONFIG_FEC_ALIGN != 0))
+#error "PKTALIGN must be multiple of CONFIG_FEC_ALIGN!" +#endif
We should keep these checks in case some obscure platform appears.
Otherwise, we're almost there Eric! Great work !!
Best regards, Marek Vasut