This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform.
This seriesl updates U-Boot existing SiFive CLINT driver to handle the ACLINT changes, and is now able to support both CLINT and ACLINT.
With this series, U-Boot is able to boot on:
- QEMU 'virt' machine with 'aclint=on' - Rocket Chip with ACLINT changes [2]
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc [2] https://github.com/chipsalliance/rocket-chip/pull/3330
Bin Meng (3): riscv: timer: Update the sifive clint timer driver to support aclint riscv: clint: Update the sifive clint ipi driver to support aclint riscv: Rename SiFive CLINT to RISC-V ALINT
MAINTAINERS | 2 +- arch/riscv/Kconfig | 12 ++- arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/fu740/Kconfig | 2 +- arch/riscv/cpu/generic/Kconfig | 4 +- arch/riscv/cpu/jh7110/Kconfig | 2 +- arch/riscv/include/asm/global_data.h | 4 +- arch/riscv/include/asm/syscon.h | 2 +- arch/riscv/lib/Makefile | 2 +- .../lib/{sifive_clint.c => aclint_ipi.c} | 31 ++++++-- board/openpiton/riscv64/Kconfig | 2 +- board/sipeed/maix/Kconfig | 2 +- drivers/timer/Makefile | 2 +- drivers/timer/riscv_aclint_timer.c | 74 +++++++++++++++++++ drivers/timer/sifive_clint_timer.c | 68 ----------------- include/configs/ae350.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/starfive-visionfive2.h | 1 + 19 files changed, 124 insertions(+), 94 deletions(-) rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (53%) create mode 100644 drivers/timer/riscv_aclint_timer.c delete mode 100644 drivers/timer/sifive_clint_timer.c