Re: [U-Boot] [PATCH] fsl-ddr: Fix some bugs in the ddr infrastructure

1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1;
2. rd_to_pre we missed to add the ADD_LAT for DDR2 case and check the min tRTP.
3. wr_to_rd add the check the min requirement for tWTR.

Reported-by: Joakim Tjernlund Joakim.Tjernlund@transmode.se Signed-off-by: Dave Liu daveliu@freescale.com

Acked-by: Joakim Tjernlund Joakim.Tjernlund@transmode.se