29 Jul
2003
29 Jul
'03
11:16 a.m.
Thomas Schäfer writes:
[SDRAM discussion deleted]
Thomas> I have another question according the CIP and BMS settings Thomas> of the HRCW. They are both set to '1' which means that Thomas> exceptions are vectored to 0x000n_nnnn and boot memory Thomas> region is located at 0x0000_0000. I tried out to set those Thomas> bits to '0', it didn't work. Why?
This depends on your memory map. What is TEXT_BASE? How do you initialise chip selects? At what flash offset do you burn U-Boot?
--
========================================================================
Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader
yuli@arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel
========================================================================