Re: [U-Boot] PCIe bridge pci memory limit register problem

Dear Danny,

In message D2CCC86D6128D043B074E2A927250D0694090D@EXMAIL.interphase.iphase.com you wrote:

So, here are the changes I did here local and am thinking that if this looks ok, then I will also need to add this to the pre-fetch logic as well.

void pciauto_postscan_setup_bridge(struct pci_controller *hose,

                  pci_dev_t dev, int sub_bus)

{

struct pci_region *pci_mem = hose->pci_mem;

struct pci_region *pci_prefetch = hose->pci_prefetch;

struct pci_region *pci_io = hose->pci_io;

unsigned int bridge_mem_base = 0;

Why do you add allthese empty lines ???

/* Configure bus number registers */

pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,

               sub_bus - hose->first_busno);



if (pci_mem) {

    /* Round memory allocator to 1MB boundary */

    pciauto_region_align(pci_mem, 0x100000);

•    /* danny, 15aug08
  
  

•     * read the the bus_lower value that was placed in the
  
  

•     * PCI_MEMORY_BASE register during pciauto_prescan_setup_bridge
  
  

•     * and check to see if anything behind it consumed memory
  
  

•     */
  
  

•    pci_hose_read_config_word(hose, dev, PCI_MEMORY_BASE,
  

&bridge_mem_base)

^^^^^^^^^^^^^^^^^^^

;

•    if((bridge_mem_base >> 16) == ((pci_mem->bus_lower &
  

0xfff00000) >> 16)

^^^^^^^^^^^^^^^^^^^^

Line wrapping.

If you want to discuss code changes, then please submit a regular patch. Please see http://www.denx.de/wiki/U-Boot/Patches for instructions.

Best regards,

Wolfgang Denk