Add implementations for 32- and 64-bit ARM.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Add new patch with the arm-specific standard passage implementation
arch/arm/cpu/armv7/cpu.c | 28 ++++++++++++++++++++++++++++ arch/arm/cpu/armv8/cpu.c | 20 ++++++++++++++++++++ 2 files changed, 48 insertions(+)
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 68807d20997..4f16ea0058a 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -18,6 +18,7 @@ #include <command.h> #include <cpu_func.h> #include <irq_func.h> +#include <passage.h> #include <asm/system.h> #include <asm/cache.h> #include <asm/armv7.h> @@ -83,3 +84,30 @@ int cleanup_before_linux(void) { return cleanup_before_linux_select(CBL_ALL); } + +void __noreturn arch_passage_entry(ulong entry_addr, ulong bloblist, ulong fdt) +{ + typedef void __noreturn (*passage_entry_t)(ulong zero1, ulong mach, + ulong fdt, ulong bloblist); + passage_entry_t entry = (passage_entry_t)entry_addr; + + /* + * Register Contents + * r0 0 + * r1 0xb0075701 (indicates standard passage v1) + * r2 Address of devicetree + * r3 Address of bloblist + * r4 0 + * lr Return address + * + * The ARMv7 calling convention only passes 4 arguments in registers, so + * set r4 to 0 manually. + */ + __asm__ volatile ( + "mov r4, #0\n" + : + : + : "r4" + ); + entry(0, passage_mach_version(), fdt, bloblist); +} diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index ea40c55dd2c..4d67152f033 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -14,6 +14,7 @@ #include <command.h> #include <cpu_func.h> #include <irq_func.h> +#include <passage.h> #include <asm/cache.h> #include <asm/system.h> #include <asm/secure.h> @@ -84,3 +85,22 @@ void armv8_setup_psci(void) secure_ram_addr(psci_arch_init)(); } #endif + +void __noreturn arch_passage_entry(ulong entry_addr, ulong bloblist, ulong fdt) +{ + typedef void __noreturn (*passage_entry_t)(ulong fdt, ulong abi, + ulong zero1, ulong bloblist, + ulong zero2); + passage_entry_t entry = (passage_entry_t)entry_addr; + + /* + * Register Contents + * x0 Address of devicetree + * x1 0xb00757a300000001 (indicates standard passage v1) + * x2 0 + * x3 Address of bloblist + * x4 0 + * x30 Return address + */ + entry(fdt, passage_mach_version(), 0, bloblist, 0); +}