in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD:
{standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'
so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL.
Signed-off-by: Heiko Schocher hs@denx.de
---
arch/arm/cpu/arm926ejs/cpu.c | 2 ++ arch/arm/lib/cache.c | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index e37e87b..a90ce30 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -45,7 +45,9 @@ int cleanup_before_linux (void) /* flush I/D-cache */ static void cache_flush (void) { +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); +#endif } diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 4e597a4..b016558 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -24,10 +24,12 @@ __weak void flush_cache(unsigned long start, unsigned long size) #endif /* CONFIG_ARM1136 */
#ifdef CONFIG_ARM926EJS +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif #endif /* CONFIG_ARM926EJS */ return; }