U-Boot cmd "cpu detail" shows inconsistent CPU features and is missing clk_request and free handlers. The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board.
Patch 1: add clk request handler to check if valid clock id is requested. Patch 2: add cpu node aliases Patch 3: Correctly parse and update mmu-type.
RISC-V core's on FU540-C000 SoC have separate instruction and data (split) L1 cache. Patch 4:Use i-cache-size dt property as one of identifier to indicate a split cache is available.
I have picked few dependent patches from Sean's and Pragnesh's latest series from here [1]...[5].
These have applied on mainline U-Boot commit 8c48bb21bd6a ("Prepare v2020.07-rc3")
Patch history: ============================================= V2: 1. Incorporate review comments from Bin and Sean Anderson. and dropped 2nd patch as similar work was already done in [1] & [2] 2 Add cpu node aliases to display cpu node's in sequence. 3. Add fix to show mmu as available cpu feature. 4. Check and append L1 cache feature.
V1: Base version. Thanks to Vincent Chen vincent.chen@sifive.com for testing the V1 version of this series.
[1] https://patchwork.ozlabs.org/patch/1295345 [2] https://patchwork.ozlabs.org/patch/1295346 [3] https://patchwork.ozlabs.org/patch/1297146 [4] https://patchwork.ozlabs.org/patch/1297147 [5] https://patchwork.ozlabs.org/patch/1297149
All these together is available here: https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v2
Sagar Shrikant Kadam (4): fu540: prci: add request and free clock handlers riscv: dts: hifive-unleashed-a00: add cpu aliases riscv: cpu: fixes to display proper CPU features riscv: cpu: check and append L1 cache to cpu features
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++ drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++ drivers/cpu/riscv_cpu.c | 10 +++++++++- 3 files changed, 35 insertions(+), 1 deletion(-)