* 829520: Code bounded by indirect conditional branch might corrupt instruction stream, Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor
* 833471: VMSR FPSCR functional failure or deadlock Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush
Signed-off-by: Ashish Kumar Ashish.Kumar@freescale.com --- arch/arm/cpu/armv8/start.S | 20 ++++++++++++++++++++ include/configs/ls2080a_common.h | 2 ++ 2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index da45d98..dd583c9 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -132,6 +132,26 @@ apply_a57_core_errata: msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif
+#ifdef CONFIG_ARM_ERRATA_833471 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* FPSCR write flush. + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 38 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_829520 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Indirect Predictor bit will prevent this erratum + from occurring + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 4 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + + #ifdef CONFIG_ARM_ERRATA_833069 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable Enable Invalidates of BTB bit */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index a503934..9ab5d97 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -18,6 +18,8 @@ /* Errata fixes */ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 +#define CONFIG_ARM_ERRATA_833471 +#define CONFIG_ARM_ERRATA_829520
#include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h>