From: Alex Marginean alexandru.marginean@nxp.com
The definition follows the DSA binding in kernel and describes the switch, its ports and PHYs. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is not used in U-Boot and was disabled. Ethernet port aliases were also added to better manage the multitude of ports available now, and to enforce the order in which master and slave ports are probed.
Signed-off-by: Alex Marginean alexandru.marginean@nxp.com Signed-off-by: Claudiu Manoil claudiu.manoil@nxp.com --- arch/arm/dts/fsl-ls1028a-rdb.dts | 36 +++++++++++++++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 55 +++++++++++++++++++++++++++++++- 2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 85b4815b2e..92d83a5c0c 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -131,9 +131,45 @@ phy-handle = <&rdb_phy0>; };
+ðsw_ports { + port@0 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy0>; + }; + port@1 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy1>; + }; + port@2 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy2>; + }; + port@3 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy3>; + }; +}; + &mdio0 { status = "okay"; rdb_phy0: phy@2 { reg = <2>; }; + + sw_phy0: phy@10 { + reg = <0x10>; + }; + sw_phy1: phy@11 { + reg = <0x11>; + }; + sw_phy2: phy@12 { + reg = <0x12>; + }; + sw_phy3: phy@13 { + reg = <0x13>; + }; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index d0850237c7..e73769392f 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -14,6 +14,17 @@ #address-cells = <2>; #size-cells = <2>;
+ aliases { + eth0 = &enetc0; + eth1 = &enetc1; + eth2 = &enetc2; + eth3 = &enetc6; + eth4 = &felix0; + eth5 = &felix1; + eth6 = &felix2; + eth7 = &felix3; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -151,9 +162,51 @@ reg = <0x000300 0 0 0 0>; status = "disabled"; }; + ethsw: pci@0,5 { + #address-cells=<0>; + #size-cells=<1>; + reg = <0x000500 0 0 0 0>; + + ethsw_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + felix0: port@0 { + reg = <0>; + status = "disabled"; + label = "swp0"; + }; + felix1: port@1 { + reg = <1>; + status = "disabled"; + label = "swp1"; + }; + felix2: port@2 { + reg = <2>; + status = "disabled"; + label = "swp2"; + }; + felix3: port@3 { + reg = <3>; + status = "disabled"; + label = "swp3"; + }; + port@4 { + reg = <4>; + phy-mode = "internal"; + status = "okay"; + ethernet = <&enetc2>; + }; + port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + }; + }; + }; enetc6: pci@0,6 { reg = <0x000600 0 0 0 0>; - status = "okay"; + status = "disabled"; phy-mode = "internal"; }; };