28 Oct
2008
28 Oct
'08
5:04 p.m.
On Tue, Oct 28, 2008 at 4:53 AM, Dave Liu daveliu@freescale.com wrote:
The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more.
Signed-off-by: Dave Liu daveliu@freescale.com
Applied, thanks
Andy