The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel o.rempel@pengutronix.de Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel o.rempel@pengutronix.de Reported-by: Russell King rmk+kernel@armlinux.org.uk Reviewed-by: Russell King rmk+kernel@armlinux.org.uk Tested-by: Russell King rmk+kernel@armlinux.org.uk Signed-off-by: David S. Miller davem@davemloft.net
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam festevam@gmail.com Reviewed-by: Michael Walle michael@walle.cc Tested-by: Tom Rini trini@konsulko.com --- Changes since v2: - None
drivers/net/phy/atheros.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 13f7275d17..f922fecd6b 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev) * Fixup for the AR8035 which only has two bits. The two * remaining bits map to the same frequencies. */ - if (phydev->drv->uid == AR8035_PHY_ID) { - u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
- priv->clk_25m_mask &= ~clear; - priv->clk_25m_reg &= ~clear; + if (phydev->drv->uid == AR8035_PHY_ID) { + priv->clk_25m_reg &= AR8035_CLK_25M_MASK; + priv->clk_25m_mask &= AR8035_CLK_25M_MASK; } }