On 11/21/19 11:29 AM, Simon Goldschmidt wrote:
On Wed, Nov 20, 2019 at 10:36 PM Marek Vasut wrote:
The NAND devices with 128 kiB erase blocks require extra 64 kiB padding between each SPL image. Generate U-Boot image with such a padding using this new target.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com
Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/Makefile b/Makefile index 7485bc2594..d3038cf665 100644 --- a/Makefile +++ b/Makefile @@ -1476,6 +1476,17 @@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ u-boot.img > $@ || rm -f $@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot)
+quiet_cmd_socnandboot = SOCNANDBOOT $@ +cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \
There's already a file 'spl/u-boot-spl-pad.bin' which is used for reserving bss between spl binary and dtb. Could we use a more speaking name here?
Like what would you propose ?