In message 1628E43D99629C46988BE46087A3FBB95C59D2@ep-01.EmbeddedPlanet.local you wrote:
SOLUTION (or at least an explanation, and it has nothing to do with the longish comment in this source file)
Oh yes, it has.
Form the MPC866 data sheet: "When the MPC866 internal core begins accessing memory at system reset, CS0 is asserted for every address, unless an internal register is accessed...CS0 operates this way until the first write to OR0 and it can be used as any other chip-select register once the preferred address range is loaded into BR0."
Standard MPC8xx init sequence, that is.
All of this is already loaded by the BDI debugger, so that is what is
Argh. Why are you doing this? I've been preaching for ages that your BDI config file should be basicly EMPTY, i. e. just contain the unavoidable stuff like disabling the watchdog. But it MUST NOT touch the memory controller. U-Boot expects a VIRGIN CPU frosh out of reset.
If you mess with it you get what you deserve.
Proposed solution: Before clearing BR0, include the following:
Wrong. Solution is: DON'T MESS THE CPU STATE before passing control to U-Boot.
The next e-mail will be a patch
It will be rejected.
Best regards,
Wolfgang Denk