Hi,
On Mon, Mar 17, 2008 at 05:32:10PM -0500, Nishanth Menon wrote:
Hi Sascha,
I think we dont have a seperate list for uboot-v2,
No we have not. This is the right place ;)
so, just wanted to know the opinion of having a single arch/arm/cpu/start-arm.S instead of multiple start-arm files. essentially providing hooks to arch,soc,board specific preinits can allow us to reuse major chunk of code.. I have attached a sample start-arm.S (modified from start-arm920t.S) as reference.
Do let me know your comments and view as to how the initial handling can be made abstract enough to plug into requirements of future SOCs, boards etc. I am looking not to mash in #ifdef ARCH_XYZ for each of the SOC implementation I plan on doing.
Regards, Nishanth Menon
It is my plan to unify the different start.S files anyway, so good idea ;)
I'll comment on a diff to current start-arm920t.S as it's easier to see what you actually changed.
diff --git a/arch/arm/cpu/start-arm920t.S b/arch/arm/cpu/start-arm920t.S index db52ad9..a2c9ecb 100644 --- a/arch/arm/cpu/start-arm920t.S +++ b/arch/arm/cpu/start-arm920t.S @@ -29,11 +29,7 @@
- @brief The very basic beginning of each CPU after reset
- @note
- This reset code can be used at least for:
- ARM920T
- i.MX1
- i.MX27
- i.MX31
- This reset code can be used at least for All ARM platforms
I wouldn't say it works at least on all arm platforms, maybe for xscale it's easier to have a start-xscale.S, but I haven't looked into this very deeply. But for sure this code won't work on any non-arm platform.
- FIXME: Stop doxygen from parsing the text below
*/ @@ -134,32 +130,26 @@ reset: #ifdef ARCH_HAS_INIT_LOWLEVEL bl arch_init_lowlevel #endif
- /*
* flush v4 I/D caches*/- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- /*
* disable MMU stuff and caches+#ifdef CONFIG_SOC_PRE_INIT
- /* Do SOC specific initalization here
* r0 contains the start address* This allows for SOC code to configure* based on current program execution context* E.g.: NOR boot Vs SDRAM boot.
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
- mov r0,pc
- bl soc_init_crit
+#endif /* CONFIG_SOC_PRE_INIT */
We do not have any SoC specific init at the moment, but when you need it lets introduce it here.
/*
* before relocating, we have to setup RAM timing* because memory timing is board-dependend, you will* find a lowlevel_init.S in your board directory.
* we do sys-critical inits only at reboot,* not when booting from ram!#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl board_init_lowlevel
- bl cpu_init_crit
#endif
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ @@ -176,6 +166,7 @@ copy_loop: stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
No need to introduce this option. Look into the various board specific lowlevel-init.S. They all check whether we run from RAM or not, so all binaries can run from RAM or ROM without changes. In case we run with start address == link address the relocation is skipped anyway.
/* Set up the stack */ stack_setup: @@ -199,6 +190,48 @@ clbss_l:str r2, [r0] /* clear loop... */
_start_armboot: .word start_uboot
+/*************************************************************************
- CPU_init_critical registers
- setup important registers
- setup memory timing
- ************************************************************************/
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit:
- /*
* flush v4 I/D caches*/- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- /*
* disable MMU stuff and caches*/- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_ARM_ALIGN_ABRT
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
+#endif +#ifdef CONFIG_ARM_I_CACHE
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
+#endif
- mcr p15, 0, r0, c1, c0, 0
- /*
* before relocating, we have to setup RAM timing* because memory timing is board-dependent, you will* find a lowlevel_init.S in your board directory.*/- mov ip, lr
- bl board_init_lowlevel
- mov lr, ip
- mov pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
Do we really need the SKIP_LOWLEVEL_INIT option? It should be safe to run all times.
Sascha