There is currently a massive bug that makes any gate clk that have CLK_XTAL as parent to return the wrong clock.
Following the code, with CLK_XTAL defined as TOPCKGEN parent, the topckgen get_rate is called. The clk ID (0) is parsed and only in some corner case (scenario where fixed clock are not defined) the correct XTAL rate will be returned as get_factor or get_mux is called (that have correct handling for CLK_XTAL). With fixed clock defined, the rate that will be returned will always be the FIRST ELEMENT of the fixed clock table instead of the hardcoded XTAL rate.
To handle this, add additional logic and if the flag is set to PARENT_XTAL for the gate, return the XTAL rate directly.
We assume the clk_tree to have xtal_rate defined with clk gates that have XTAL as parents.
Signed-off-by: Christian Marangi ansuelsmth@gmail.com --- drivers/clk/mediatek/clk-mtk.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d2c45be30de..e68beccc060 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -543,6 +543,13 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate = &priv->gates[clk->id];
+ /* + * Assume xtal_rate to be declared if some gates have + * XTAL as parent + */ + if (gate->flags & CLK_PARENT_XTAL) + return priv->tree->xtal_rate; + return mtk_clk_find_parent_rate(clk, gate->parent, priv->parent); }