This patchset add the fastboot support for rk3288, and I have tested on firefly-rk3288 & evb-rk3288 board.
Fix an issue which was mentioned in V1's cover-letter: The DMA buffer was always zero after DMA transmission is compete, it takes no effect that invalidate dcache after DMA transfer completed and before the CPU readed. It's important to invalidate dcache before starting DMA, ensure coherency and prevent from any dirty lines in the cache which from the DMA buffer.
Changes in v4: - Implement a mechanism to be compatible with more Rockchip SoCs - Rename rockchip_usb_syno_phy.c to rockchip_usb2_phy.c - Rework fifo size getting and setting - Update commit message - Add fifo size for rk3288 - Get usb_phy's dt_node
Changes in v3: - Make UOC_CON registers to be unfixed which should be got from DT - Achieve UOC_CON_OFFSET physical address from DT - New commit since v3 to fix the coherence issue between memory and cache
Changes in v2: - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c - Rework the behaviour in otg_phy_init() and otg_phy_off() - Update detailed commit message - Modify the macro's values - Achieve the regs_phy from DT - Update comments a little
Xu Ziyuan (4): usb: rockchip-phy: implement USB2.0 phy control usb: dwc2-otg: adjust fifo size via platform data rockchip: rk3288: add fastboot support usb: dwc2 : invalidate dcache before starting DMA
arch/arm/dts/rk3288.dtsi | 1 + arch/arm/mach-rockchip/board.c | 72 +++++++++++++++++++ drivers/usb/gadget/dwc2_udc_otg.c | 22 ++++-- drivers/usb/gadget/dwc2_udc_otg_regs.h | 6 +- drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 + drivers/usb/phy/Makefile | 1 + drivers/usb/phy/rockchip_usb2_phy.c | 107 +++++++++++++++++++++++++++++ include/configs/rk3288_common.h | 26 +++++++ include/usb/dwc2_udc.h | 5 ++ 9 files changed, 234 insertions(+), 9 deletions(-) create mode 100644 drivers/usb/phy/rockchip_usb2_phy.c