Re: [U-Boot] [PATCH] arm: zynq: Label whole PL part as fpga_full region

On 29.6.2017 19:38, Moritz Fischer wrote:

Hi Michal,

can you / did you send this to the kernel ML, too?

We need to send fpga manager driver first but yes we will do it.

On Thu, Jun 29, 2017 at 3:14 AM, Michal Simek michal.simek@xilinx.com wrote:

...

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek michal.simek@xilinx.com

Reviewed-by: Moritz Fischer moritz.fischer@ettus.com

Thanks, Michal