PS The RX errors generated by switching from the Broadcom Ethernet chips to the National Ethernet chips are specifically RxBD_CRCERR and RxBD_NO (defined in uec.h). These errors are frame CRC error and Non-octet align errors respectively.
Thanks.
Christopher M. Fairfax Sr. Software Engineer Rockwell Collins +1 540-428-3344 +1 540-428-3301 cmfairfa@rockwellcollins.com This message contains PRIVILEGED AND PROPRIETARY INFORMATION intended solely for the use of the addressee(s) named above. Any disclosure, distribution, copying or use of the information by others is strictly prohibited. If you have received this message in error, please advise the sender by immediate reply and delete the original message. Thank you.
Christopher M Fairfax/USA/RockwellCollins 06/23/2009 01:35 PM
To u-boot@lists.denx.de cc avorontsov@ru.mvista.com Subject MPC8360ERDK U-Boot - Broadcom Gigabit Ethernet removal
Hi, I'm trying to completely remove the 2 gigabit ethernets from my U-Boot (as they are depopulated on my target). I want to use the other 2 ethernet ports as FSL UEC0 and FSL UEC1. I've removed the UCC1 and UCC2 entries from the qe_iop_conf_tab in mpc8360erdk.c and updated the corresponding macros in MPC8360ERDK.h. The transmits seem to work. I'm able to communicate from the target to a TFTP server on a PC. However, the RX to the target is not working. I get "FSL UEC: Rx error" messages.
Any ideas/suggestions as to what I need to do to get the RX to work?
Also, do I need to define CFG_CMD_MII and/or CFG_MII, so that miiphy_register() is called in uec.c
Here are my new macro definitions in MPC8360ERDK.h:
#define CONFIG_UEC_ETH1 /* GETH1 */
#ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 6 /* UCC7 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK19 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK20 #define CONIFG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 1 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII #endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#ifdef CONFIG_UEC_ETH2 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 #define CONIFG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 3 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII #endif
Thanks
Christopher M. Fairfax Sr. Software Engineer Rockwell Collins +1 540-428-3344 +1 540-428-3301 cmfairfa@rockwellcollins.com This message contains PRIVILEGED AND PROPRIETARY INFORMATION intended solely for the use of the addressee(s) named above. Any disclosure, distribution, copying or use of the information by others is strictly prohibited. If you have received this message in error, please advise the sender by immediate reply and delete the original message. Thank you.