On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:
On 03/16/2016 09:59 AM, Wills Wang wrote:
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection.
Signed-off-by: Wills Wang wills.wang@live.com
Changes in v8:
- Use setbits_be32
- Use lookup-table instead of big switch statement for CPU detection
Good stuff, minor nits below.
+++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,142 @@ +/*
- Copyright (C) 2015-2016 Wills Wang wills.wang@live.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h>
+struct ath79_soc_desc {
- enum ath79_soc_type soc;
- const char *chip;
- int major;
- int minor;
All of this stuff can be const, no ?
OK.
+};
[...]
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..c29e98c --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,16 @@ +/*
- Copyright (C) 2015-2016 Wills Wang wills.wang@live.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <linux/sizes.h> +#include <asm/addrspace.h> +#include <mach/ddr.h>
+phys_size_t initdram(int board_type) +{
- ddr_tap_tuning();
Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
Yes, it's for optimizing DDR timing according to hardware. Sometimes, the hard code value is not ideal.
- return get_ram_size((void *)KSEG1, SZ_256M);
+} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..893dedc --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -0,0 +1,1184 @@ +/*
- Atheros AR71XX/AR724X/AR913X SoC register definitions
- Copyright (C) 2015-2016 Wills Wang wills.wang@live.com
- Copyright (C) 2010-2011 Jaiganesh Narayanan jnarayanan@atheros.com
- Copyright (C) 2008-2010 Gabor Juhos juhosg@openwrt.org
- Copyright (C) 2008 Imre Kaloz kaloz@openwrt.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H
+#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT(nr) (1 << (nr))
This should really go into some common header.
This header is also included by some assembly code, but the BIT macro in linux/bitops.h isn't compatiable with assembler.
+#endif +#endif
+#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000
Indent the macro value with tabs in this file please.
[...]