Re-enabling OCRAM ECC can cause some value changes in SRAM. Just clear fake interrupt status and keep other bits intact.
Signed-off-by: Jian Luo jian.luo4@boschrexroth.de --- Changes for v2: - add CC to custodian
arch/arm/mach-socfpga/spl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..c858406 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -90,12 +90,14 @@ void board_init_f(ulong dummy) * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); - if (reg & SYSMGR_ECC_OCRAM_SERR) - writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); - if (reg & SYSMGR_ECC_OCRAM_DERR) - writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) { + reg &= ~SYSMGR_ECC_OCRAM_SERR; + writel(reg, &sysmgr_regs->eccgrp_ocram); + } + if (reg & SYSMGR_ECC_OCRAM_DERR) { + reg &= ~SYSMGR_ECC_OCRAM_DERR; + writel(reg, &sysmgr_regs->eccgrp_ocram); + }
memset(__bss_start, 0, __bss_end - __bss_start);