Two minor issues arise as warning during boot phases once log features and CONFIG_LOG_ERROR_RETURN are enabled:
- clk_get_rate() return err (SPL, pre relocation and U-Boot proper phases) - uclass_get_device_by_phandle_id() return err (pre relocation phase only)
Both issues are not fatal and do not cause any functional problem, anyway they are fixed with these patches. Moreover, the support added in RK3308 clock driver to get UARTs rate makes 'clock-frequency' property useless in RK3308 based boards *-u-boot.dtsi files: due to the fact that UART is inited by an external TPL, in other boot phases (SPL, U-Boot proper) there is no need to know UART clock from DT but get it just reading how external TPL has configured SoC registers.
<debug_uart> s() returning err=-2
U-Boot SPL 2023.07-00560-gf2090b144c (Jul 27 2023 - 16:27:11 +0200) Trying to boot from MMC1 INFO: Preloader serial: 0 NOTICE: BL31: v1.3(release):30f1405 NOTICE: BL31: Built : 17:08:28, Sep 23 2019 INFO: Lastlog: last=0x100000, realtime=0x102000, size=0x2000 INFO: ARM GICv2 driver initialized INFO: Using opteed sec cpu_context! INFO: boot cpu mask: 1 INFO: plat_rockchip_pmu_init: pd status 0xe b INFO: BL31: Initializing runtime services WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK ERROR: Error initializing runtime service opteed_fast INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x600000 INFO: SPSR = 0x3c9
<debug_uart> clk_get_rate() returning err=-2 pinctrl_select_state_full() ns16550_serial serial@ff0a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 pinctrl_select_state_full() ns16550_serial serial@ff0a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 pinctrl_select_state_full() ns16550_serial serial@ff0a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
U-Boot 2023.07-00560-gf2090b144c (Jul 27 2023 - 16:27:11 +0200)
Model: Radxa ROCK Pi S DRAM: 512 MiB (effective 510 MiB) clk_get_rate() returning err=-2 Core: 287 devices, 23 uclasses, devicetree: separate MMC: mmc@ff480000: 1, mmc@ff490000: 0, mmc@ff4a0000: 2
Massimo Pegorer (3): clk: rockchip: rk3308: Fix ordering between masking and shifting clk: rockchip: rk3308: Support reading UART rate and clock registers dts: rockchip: rk3308: Avoid warning for serial probe on prereloc
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 29 +++++++- arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 15 ++++ drivers/clk/rockchip/clk_rk3308.c | 69 +++++++++++++++++-- 3 files changed, 106 insertions(+), 7 deletions(-)