-----Original Message----- From: Holger Brunck holger.brunck@ch.abb.com Sent: Tuesday, November 26, 2019 11:39 PM To: u-boot@lists.denx.de Cc: Holger Brunck holger.brunck@ch.abb.com; Priyanka Jain priyanka.jain@nxp.com; Valentin Longchamp valentin.longchamp@ch.abb.com Subject: [PATCH 1/4] ppc/km/tegr1: support second localbus clock signal
On kmtegr1 we have to specify the second localbus clock signal also instead of using the default for our ppc 8309 boards.
Signed-off-by: Holger Brunck holger.brunck@ch.abb.com CC: Priyanka Jain priyanka.jain@nxp.com CC: Valentin Longchamp valentin.longchamp@ch.abb.com
include/configs/km/km-mpc8309.h | 2 ++ include/configs/kmtegr1.h | 17 +++++++++++++++++ 2 files changed, 19 insertions(+)
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km- mpc8309.h index 9aaea273e0..e710c04493 100644 --- a/include/configs/km/km-mpc8309.h +++ b/include/configs/km/km-mpc8309.h @@ -22,6 +22,7 @@
- System IO Config
*/ /* 0x14000180 SICR_1 */ +#ifndef CONFIG_SYS_SICRL #define CONFIG_SYS_SICRL (0 \ | SICR_1_UART1_UART1RTS \ | SICR_1_I2C_CKSTOP \ @@ -38,6 +39,7 @@ | SICR_1_FEC1_FEC1 \ | SICR_1_FEC2_FEC2 \ ) +#endif
/* 0x00080400 SICR_2 */ #define CONFIG_SYS_SICRH (0 \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index e627606222..a441fca121 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -30,6 +30,23 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_SICRL (0 \
| SICR_1_UART1_UART1RTS \| SICR_1_I2C_CKSTOP \| SICR_1_IRQ_A_IRQ \| SICR_1_IRQ_B_IRQ \| SICR_1_GPIO_A_GPIO \| SICR_1_GPIO_B_GPIO \| SICR_1_GPIO_C_GPIO \| SICR_1_GPIO_D_GPIO \| SICR_1_GPIO_E_LCS \| SICR_1_GPIO_F_GPIO \| SICR_1_USB_A_UART2S \| SICR_1_USB_B_UART2RTS \| SICR_1_FEC1_FEC1 \| SICR_1_FEC2_FEC2 \- )
/* include common defines/options for all Keymile boards */ #include "km/keymile-common.h"
#include "km/km-powerpc.h"
2.24.0.rc1
Series applied on u-boot-mpc85xx. Awaiting upstream Thanks Priyanka