The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific to e500.
Signed-off-by: Kumar Gala galak@kernel.crashing.org ---
Note since this patch is larged, I've cut out all but one board file in the diff at this point. The real patch can be found here:
http://git.kernel.org/git/?p=boot/u-boot/galak/u-boot.git;a=commitdiff;h=ea4...
or
git.kernel.org:/pub/scm/boot/u-boot/galak/u-boot.git mpc85xx
board/freescale/mpc8540ads/init.S | 145 +++++++++++++++++-------------------- board/freescale/mpc8541cds/init.S | 124 ++++++++++++++----------------- board/freescale/mpc8544ds/init.S | 117 +++++++++++++----------------- board/freescale/mpc8548cds/init.S | 109 +++++++++++++--------------- board/freescale/mpc8555cds/init.S | 124 ++++++++++++++----------------- board/freescale/mpc8560ads/init.S | 144 +++++++++++++++++-------------------- board/freescale/mpc8568mds/init.S | 104 ++++++++++++-------------- board/mpc8540eval/init.S | 132 +++++++++++++++++----------------- board/pm854/init.S | 124 ++++++++++++++----------------- board/pm856/init.S | 124 ++++++++++++++----------------- board/sbc8560/init.S | 94 ++++++++++++------------ board/stxgp3/init.S | 144 +++++++++++++++++-------------------- board/stxssa/init.S | 110 +++++++++++++---------------- board/tqm85xx/init.S | 124 ++++++++++++++----------------- cpu/mpc85xx/spd_sdram.c | 23 +++---- include/asm-ppc/mmu.h | 13 ++++ include/e500.h | 88 ---------------------- 17 files changed, 809 insertions(+), 1034 deletions(-)
diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S index 544fde9..74d71c6 100644 --- a/board/freescale/mpc8540ads/init.S +++ b/board/freescale/mpc8540ads/init.S @@ -43,7 +43,7 @@ * * MAS0: tlbsel, esel, nv * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS2: epn, x0, x1, w, i, m, g, e * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr */
@@ -75,10 +75,10 @@ tlb1_entry: * This ends up at a TLB0 Index==0 entry, and must not collide * with other TLB0 Entries. */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) #else #error("Update the number of table entries in tlb1_entry") #endif @@ -94,112 +94,99 @@ tlb1_entry: * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 0: 16M Non-cacheable, guarded * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 0, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 1, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 2, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 3, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 4, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 5, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 6, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) + .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/* * TLB 7: 16K Non-cacheable, guarded * 0xf8000000 16K BCSR registers */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 7, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) + .long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM) /* @@ -211,17 +198,15 @@ tlb1_entry: * Likely it needs to be increased by two for these entries. */ #error("Update the number of table entries in tlb1_entry") - .long TLB1_MAS0(1, 8, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1, 9, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 8, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) + .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(1, 9, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) + .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) #endif
entry_end
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 553f736..adc9c4d 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); - mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0)); + mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); asm volatile("isync;msync;tlbwe;isync");
- debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", - TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0)); debug("DDR: MAS3=0x%08x\n", - TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR)));
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b77cf8f..eb87184 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -388,6 +388,19 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define MAS7_RPN 0xFFFFFFFF
+#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ + (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) +#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ + ((((v) << 31) & MAS1_VALID) |\ + (((iprot) << 30) & MAS1_IPROT) |\ + (MAS1_TID(tid)) |\ + (((ts) << 12) & MAS1_TS) |\ + (MAS1_TSIZE(tsize))) +#define FSL_BOOKE_MAS2(epn, wimge) \ + (((epn) & MAS3_RPN) | (wimge)) +#define FSL_BOOKE_MAS3(rpn, user, perms) \ + (((rpn) & MAS3_RPN) | (user) | (perms)) + #define BOOKE_PAGESZ_1K 0 #define BOOKE_PAGESZ_4K 1 #define BOOKE_PAGESZ_16K 2 diff --git a/include/e500.h b/include/e500.h index 983826d..1971eee 100644 --- a/include/e500.h +++ b/include/e500.h @@ -17,94 +17,6 @@ typedef struct
#endif /* _ASMLANGUAGE */
-/* Motorola E500 core provides 16 TLB1 entries; they can be used for - * initial memory mapping like legacy BAT registers do. Usually we - * use four MAS registers(MAS0-3) to operate on TLB1 entries. - * - * While there are 16 Entries with variable Page Sizes in TLB1, - * there are also 256 Entries with fixed 4K pages in TLB0. - * - * We also need LAWs(Local Access Window) to associate a range of - * the local 32-bit address space with a particular target interface - * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM. - * - * We put TLB1/LAW code here because memory mapping is board-specific - * instead of cpu-specific. - * - * While these macros are all nominally for TLB1 by name, they can - * also be used for TLB0 as well. - */ - - -/* - * Convert addresses to Effective and Real Page Numbers. - * Grab the high 20-bits and shift 'em down, dropping the "byte offset". - */ -#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff) -#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff) - - -/* MAS0 - * tlbsel(TLB Select):0,1 - * esel(Entry Select): 0,1,2,...,15 for TLB1 - * nv(Next victim):0,1 - */ -#define TLB1_MAS0(tlbsel,esel,nv) \ - (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) - -/* MAS1 - * v(TLB valid bit):0,1 - * iprot(invalidate protect):0,1 - * tid(translation identity):8bit to match process IDs - * ts(translation space,comparing with MSR[IS,DS]): 0,1 - * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M) - */ -#define TLB1_MAS1(v,iprot,tid,ts,tsize) \ - ((((v) << 31) & MAS1_VALID) |\ - (((iprot) << 30) & MAS1_IPROT) |\ - (MAS1_TID(tid)) |\ - (((ts) << 12) & MAS1_TS) |\ - (MAS1_TSIZE(tsize))) - -/* MAS2 - * epn(effective page number):20bits - * sharen(Shared cache state):0,1 - * x0,x1(implementation specific page attribute):0,1 - * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded, - * endianness):0,1 - */ -#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ - ((((epn) << 12) & MAS2_EPN) |\ - (((x0) << 6) & MAS2_X0) |\ - (((x1) << 5) & MAS2_X1) |\ - (((w) << 4) & MAS2_W) |\ - (((i) << 3) & MAS2_I) |\ - (((m) << 2) & MAS2_M) |\ - (((g) << 1) & MAS2_G) |\ - (e) ) - -/* MAS3 - * rpn(real page number):20bits - * u0-u3(user bits, useful for page table management in OS):0,1 - * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read, - * write,execute permission). - */ -#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \ - ((((rpn) << 12) & MAS3_RPN) |\ - (((u0) << 9) & MAS3_U0) |\ - (((u1) << 8) & MAS3_U1) |\ - (((u2) << 7) & MAS3_U2) |\ - (((u3) << 6) & MAS3_U3) |\ - (((ux) << 5) & MAS3_UX) |\ - (((sx) << 4) & MAS3_SX) |\ - (((uw) << 3) & MAS3_UW) |\ - (((sw) << 2) & MAS3_SW) |\ - (((ur) << 1) & MAS3_UR) |\ - (sr) ) - - #define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */
#endif /* __E500_H__ */