From: Peng Fan peng.fan@nxp.com
The PLL clk needs use anatop base, otherwise wrong PLL address will be used.
Fixes: 9c153e46661b ("clk: imx: add i.MX93 CCF driver") Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index ce10d795316..f0cb797d975 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -289,7 +289,7 @@ static int imx93_clk_probe(struct udevice *dev) clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2, imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
- base = (void *)ANATOP_BASE_ADDR; + anatop_base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX93_CLK_ARM_PLL, imx_clk_fracn_gppll_integer("arm_pll", "clock-osc-24m",