Hi,
On 20.7.2018 18:17, Luis Araneda wrote:
Hi Michal,
On Fri, Jul 20, 2018 at 6:38 AM Michal Simek michal.simek@xilinx.com wrote:
On 20.7.2018 01:37, Luis Araneda wrote:
Hi Michal,
On Thu, Jul 19, 2018 at 2:23 AM Michal Simek michal.simek@xilinx.com wrote:
We need that functionality first but then enable it for all boards is fine for me and via one patch.
Ok
Can you please be more specific what time1/time2 and time3 means?
The exact location of time 1/2/3 are on the attached diff file, and they are placed within the spl_load_simple_fit() function. They represent, roughly:
- time1: Time to load the the FIT image
- time2: Time to extract (and decompress) the FPGA image from the FIT image
- time3: Time to program the FPGA
Sorry I missed that attachment.
First of all I have sent patch for that gzip.
On zc706 with 13MB bitstream size this looks much better.
file size (bytes) time1 time2 time3 uncompressed 13869613 2533 2694 4422 compressed -9 599149 144 765 2491
This is SD boot mode and initial time depends on SD you use.
Thanks, Michal