Dear matthias.fuchs@esd.eu,
In message 12480849383077-git-send-email-matthias.fuchs@esd.eu you wrote:
This patch migrates 4xx code from using the lowercase tcr macro to the uppercase TCR macro. Both macros have been defined in the past. So one is to much and uppercase macros are much more common.
I think this should not be TCR either. This should be SPRN_TCR as defined in <asm/processor.h>.
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 582c781..22bc409 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -626,7 +626,7 @@ _start: mtspr tbl,r0 /* prevent fit & wdt exceptions */ mtspr tbu,r0 mtspr tsr,r1 /* clear all timer exception status */
- mtspr tcr,r0 /* disable all */
- mtspr TCR,r0 /* disable all */ mtspr esr,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */
Now this mix of lower case and upper case names is really ugly, isn't it?
diff --git a/include/ppc405.h b/include/ppc405.h index 917afec..50fc7be 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -61,7 +61,6 @@ #define dear 0x3d5 /* data exeption address register */ #define evpr 0x3d6 /* exeption vector prefix register */ #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */ #define pit 0x3db /* programmable interval timer */ #define sgr 0x3b9 /* storage guarded reg */ #define dcwr 0x3ba /* data cache write-thru reg*/
diff --git a/include/ppc440.h b/include/ppc440.h index 01f6eaf..df78eea 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -90,7 +90,6 @@ #define dvc1 0x13e /* data value compare 1 */ #define dvc2 0x13f /* data value compare 2 */ #define tsr 0x150 /* timer status register */ -#define tcr 0x154 /* timer control register */ #define ivor0 0x190 /* interrupt vector offset register 0 */ #define ivor1 0x191 /* interrupt vector offset register 1 */ #define ivor2 0x192 /* interrupt vector offset register 2 */
I think all these can be dumped - they should be taken from <asm/processor.h> instead.
Best regards,
Wolfgang Denk