- Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output
== Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC
== After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- cpu/mpc86xx/cpu.c | 82 +++++++++++++++++++++--------------------- include/asm-ppc/processor.h | 8 ++++- 2 files changed, 48 insertions(+), 42 deletions(-)
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index b2a107d..c41616d 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -50,49 +50,25 @@ checkcpu(void) uint pvr, svr; uint ver; uint major, minor; + char buf1[32], buf2[32]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; - - puts("Freescale PowerPC\n"); - - pvr = get_pvr(); - ver = PVR_VER(pvr); - major = PVR_MAJ(pvr); - minor = PVR_MIN(pvr); - - puts("CPU:\n"); - puts(" Core: "); - - switch (ver) { - case PVR_VER(PVR_86xx): - { - uint msscr0 = mfspr(MSSCR0); - printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); - if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) - puts("\n Core1Translation Enabled"); - debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); - } - break; - default: - puts("Unknown"); - break; - } - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + uint msscr0 = mfspr(MSSCR0);
svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr);
- puts(" System: "); + puts("CPU: "); + switch (ver) { case SVR_8641: - if (SVR_SUBVER(svr) == 1) { - puts("8641D"); - } else { puts("8641"); - } - break; + break; + case SVR_8641D: + puts("8641D"); + break; case SVR_8610: puts("8610"); break; @@ -101,26 +77,50 @@ checkcpu(void) break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + puts("Core: "); + + pvr = get_pvr(); + ver = PVR_E600_VER(pvr); + major = PVR_E600_MAJ(pvr); + minor = PVR_E600_MIN(pvr); + + printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); + if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) + puts("\n Core1Translation Enabled"); + debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
- puts(" Clocks: "); - printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); - printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); - printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + puts("Clock Configuration:\n"); + printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); + printf(" DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, sysinfo.freqSystemBus / 2), + strmhz(buf2, sysinfo.freqSystemBus));
if (sysinfo.freqLocalBus > LCRR_CLKDIV) { - printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000); + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); }
- puts(" L2: "); - if (get_l2cr() & 0x80000000) - puts("Enabled\n"); - else + puts("L1: D-cache 32 KB enabled\n"); + puts(" I-cache 32 KB enabled\n"); + + puts("L2: "); + if (get_l2cr() & 0x80000000) { +#if defined(CONFIG_MPC8610) + puts("256"); +#elif defined(CONFIG_MPC8641) + puts("512"); +#endif + puts(" KB enabled\n"); + } else { puts("Disabled\n"); + }
return 0; } diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e07e5d3..186cd5a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -777,6 +777,13 @@ #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
+/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + /* Processor Version Numbers */
#define PVR_403GA 0x00200000 @@ -857,7 +864,6 @@ #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
#define PVR_86xx 0x80040000 -#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
#define PVR_VIRTEX5 0x7ff21912