10 Oct
2018
10 Oct
'18
8:35 a.m.
On Mon, Oct 8, 2018 at 1:08 PM Maxime Ripard maxime.ripard@bootlin.com wrote:
On Sat, Oct 06, 2018 at 11:23:32PM +0800, Icenowy Zheng wrote:
Currently the DRAM bus gate and reset is changed at the same time in H6 DRAM initialization code, which disobeys the user manual's programming guide.
Fix the sequence by follow the sequence suggested by the user manual (ungate the bus clock after release the reset signal).
By some experiments it seems to fix the DRAM size detection failure that rarely happens.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Applied to u-boot-sunxi/master