13 Sep
2017
13 Sep
'17
10:07 p.m.
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). Saradc integer divider control register is 8-bits width.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk3399.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com