From: Denis Zalevskiy denis.zalevskiy@ge.com
DM for PCI pulls DM for ethernet that also needs other changes described below to build u-boot and keep existing functionality - ability to update MAC addresses of FEC ethernet adapter and I210 adapter connected to the Marvell switch.
- fec_mxc driver with DM needs PHYLIB;
- configuration items are moved from ge_bx50v3.h to ge_bx50v3_defconfig;
- FEC is marked as eth0 because it is always present, so indices changed: I210 are still probed in the same order;
- board_eth_init() was used by legacy ethernet, setup for enet iomux and pcie is moved to the board_late_init();
- pci_init() is called from the board_late_init() to initiate PCI bus probing, so I210 devices are propagated to the device tree;
Signed-off-by: Denis Zalevskiy denis.zalevskiy@ge.com [Describe PHY reset in device tree] Signed-off-by: Ian Ray ian.ray@ge.com Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx6q-bx50v3.dts | 54 +++++++++++++++++++++++++ board/ge/bx50v3/bx50v3.c | 75 ++++++----------------------------- configs/ge_bx50v3_defconfig | 8 ++++ include/configs/ge_bx50v3.h | 12 ------ 4 files changed, 75 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index deaec63509..28a35394f0 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -13,6 +13,11 @@ / { model = "General Electric Bx50v3"; compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q"; + + aliases { + ethernet0 = &fec; + }; + };
&iomuxc { @@ -48,6 +53,30 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 >; }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* FEC Reset */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + /* AR8033 Interrupt */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; };
&usdhc1 { @@ -87,3 +116,28 @@ reg = <0>; }; }; + +&fec { + reg = <0x02188000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; + phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&pcie { + status = "okay"; +}; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 55fbcbcc81..87e34cf1c9 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -34,6 +34,8 @@ #include "../common/ge_common.h" #include "../common/vpd_reader.h" #include "../../../drivers/net/e1000.h" +#include <pci.h> + DECLARE_GLOBAL_DATA_PTR;
static int confidx = 3; /* Default to b850v3. */ @@ -81,38 +83,6 @@ static iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), };
-static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - /* AR8033 PHY Reset */ - MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* Reset AR8033 PHY */ - gpio_request(IMX_GPIO_NR(1, 28), "fec_rst"); - gpio_direction_output(IMX_GPIO_NR(1, 28), 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(1, 28), 1); - mdelay(1); -} - static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, @@ -152,16 +122,6 @@ static struct i2c_pads_info i2c_pad_info3 = { } };
-static iomux_v3_cfg_t const pcie_pads[] = { - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_pcie(void) -{ - imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); -} - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); @@ -453,7 +413,7 @@ static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
static void process_vpd(struct vpd_cache *vpd) { - int fec_index = -1; + int fec_index = 0; int i210_index = -1;
if (!vpd->is_read) { @@ -461,41 +421,30 @@ static void process_vpd(struct vpd_cache *vpd) return; }
+ if (vpd->has & VPD_HAS_MAC1) + eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1); + + env_set("ethact", "eth0"); + switch (vpd->product_id) { case VPD_PRODUCT_B450: env_set("confidx", "1"); - i210_index = 0; - fec_index = 1; + i210_index = 1; break; case VPD_PRODUCT_B650: env_set("confidx", "2"); - i210_index = 0; - fec_index = 1; + i210_index = 1; break; case VPD_PRODUCT_B850: env_set("confidx", "3"); - i210_index = 1; - fec_index = 2; + i210_index = 2; break; }
- if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) - eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1); - if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2)) eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2); }
-int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - setup_pcie(); - - e1000_initialize(bis); - - return cpu_eth_init(bis); -} - static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), @@ -649,6 +598,8 @@ int board_late_init(void)
check_time();
+ pci_init(); + return 0; }
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 0b45105134..cd0bf5bab5 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -66,3 +66,11 @@ CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_PNP=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_FEC_MXC=y +CONFIG_ETHPRIME="FEC" diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 92a927bb82..d572424831 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -49,16 +49,6 @@ #define CONFIG_USB_GADGET_MASS_STORAGE #endif
-/* Networking Configs */ -#ifdef CONFIG_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 -#define CONFIG_PHY_ATHEROS -#endif - /* Serial Flash */
/* allow to overwrite serial and ethaddr */ @@ -197,8 +187,6 @@
#define CONFIG_IMX6_PWM_PER_CLK 66000000
-#define CONFIG_PCI -#define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)