- Copyright (C) 2008,2009 Eric Jarrige jorasse@users.sourceforge.net
- Copyright (C) 2009 Ilya Yanok yanok@emcraft.com
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h>
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_MXC_UART +static void imx27lite_uart_init() +{
- int i;
- unsigned int mode[] = {
PE12_PF_UART1_TXD,PE13_PF_UART1_RXD,- };
- for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);+} +#endif /* CONFIGL_MXC_UART */
+#ifdef CONFIG_FEC_MXC +static void imx27lite_fec_init() +{
- struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
- int i;
- unsigned int mode[] = {
PD0_AIN_FEC_TXD0,PD1_AIN_FEC_TXD1,PD2_AIN_FEC_TXD2,PD3_AIN_FEC_TXD3,PD4_AOUT_FEC_RX_ER,PD5_AOUT_FEC_RXD1,PD6_AOUT_FEC_RXD2,PD7_AOUT_FEC_RXD3,PD8_AF_FEC_MDIO,PD9_AIN_FEC_MDC | GPIO_PUEN,PD10_AOUT_FEC_CRS,PD11_AOUT_FEC_TX_CLK,PD12_AOUT_FEC_RXD0,PD13_AOUT_FEC_RX_DV,PD14_AOUT_FEC_CLR,PD15_AOUT_FEC_COL,PD16_AIN_FEC_TX_ER,PF23_AIN_FEC_TX_EN,(GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31),- };
- for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);- writel(readl(®s->port[PORTC].dr) | (1 << 31),
®s->port[PORTC].dr);+} +#endif /* CONFIG_FEC_MXC */
+#ifdef CONFIG_MXC_MMC +static void imx27lite_sd_init() +{
- int i;
- unsigned int mode[] = {
PB4_PF_SD2_D0,PB5_PF_SD2_D1,PB6_PF_SD2_D2,PB7_PF_SD2_D3,PB8_PF_SD2_CMD,PB9_PF_SD2_CLK,- };
- for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);+} +#endif /* CONFIG_MXC_MMC */
tks for the udpate but the init function are not board specific but soc specific please move the to cpu/arm926ejs/soc/something.c
+int board_init (void) +{
- gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
- gd->bd->bi_boot_params = 0xa0000100;
please BASE + 0x100;
+#ifdef CONFIG_MXC_UART
- imx27lite_uart_init();
+#endif +#ifdef CONFIG_FEC_MXC
- imx27lite_fec_init();
+#endif +#ifdef CONFIG_MXC_MMC
- imx27lite_sd_init();
+#endif
- return 0;
+}
+int dram_init (void) +{
+#if CONFIG_NR_DRAM_BANKS > 0
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);+#endif +#if CONFIG_NR_DRAM_BANKS > 1
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);+#endif
- return 0;
+}
+int checkboard(void) +{
- printf("LogicPD imx27lite\n");
- return 0;
+} diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S new file mode 100644 index 0000000..e2cdecb --- /dev/null
<snip>
+#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ +#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
+#define MPCTL0_VAL 0x1ef15d5
+#define SPCTL0_VAL 0x043a1c09
+#define CSCR_VAL 0x33f08107
+#define PCDR0_VAL 0x120470c3 +#define PCDR1_VAL 0x03030303 +#define PCCR0_VAL 0xffffffff +#define PCCR1_VAL 0xfffffffc
+#define AIPI1_PSR0_VAL 0x20040304 +#define AIPI1_PSR1_VAL 0xdffbfcfb +#define AIPI2_PSR0_VAL 0x07ffc200 +#define AIPI2_PSR1_VAL 0xffffffff
+/*
- Memory Info
- */
+/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256 * 1024)
please do not mix hexa and decimal
+/* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +/* memtest start address */ +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */ +#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
+/*
- Serial Driver info
- */
+#define CONFIG_MXC_UART +#define CONFIG_SYS_MX27_UART1 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*
- Flash & Environment
- */
+#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ +/* end of flash */ +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) +/* CS2 Base address */ +#define PHYS_FLASH_1 0xc0000000 +/* Flash Base for U-Boot */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +/* Flash size 2MB */ +#define PHYS_FLASH_SIZE 0x200000 +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
CONFIG_SYS_FLASH_SECT_SZ)+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+/*
- Ethernet
- */
+#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII +#define CONFIG_NET_MULTI
+/*
- MTD
- */
+#define CONFIG_MTD_DEVICE
+/*
- NAND
- */
+#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC
+/*
- SD/MMC
- */
+#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 +#define CONFIG_DOS_PARTITION
+/*
- MTD partitions
- */
+#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0" +#define MTDPARTS_DEFAULT \
- "mtdparts=" \
"physmap-flash.0:" \"256k(U-Boot)," \"1664k(user)," \"64k(env1)," \"64k(env2);" \"mxc_nand.0:" \"128k(IPL-SPL)," \"4m(kernel)," \"22m(rootfs)," \"-(userfs)"+/*
- U-Boot general configuration
- */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer sz */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP
+/*
- U-Boot commands
- */
+#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING
you redefine cmd that are defined in the default
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
why 2?
Best Regards, J.