Re: [PATCH v5 5/6] rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

On Wed, Jun 03, 2020 at 02:43:44PM +0200, Marek Szyprowski wrote:

Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address.

Signed-off-by: Marek Szyprowski m.szyprowski@samsung.com

Applied to u-boot/master, thanks!