On Wed, Apr 10, 2024 at 9:53 PM Sean Anderson seanga2@gmail.com wrote:
On 3/7/24 19:04, Sam Protsenko wrote:
Sometimes clocks provided to a consumer might not have .set_rate operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag set. In that case it's usually possible to find a parent up the tree which is capable of setting the rate (div, pll, etc). Implement a simple lookup procedure for such cases, to traverse the clock tree until .set_rate capable parent is found, and use that parent to actually change the rate. The search will stop once the first .set_rate capable clock is found, which is usually enough to handle most cases.
Signed-off-by: Sam Protsenko semen.protsenko@linaro.org
[snip]
Can you give an example of where this is needed?
Sure. In my case it's needed for eMMC enablement on E850-96 board. eMMC node in the device tree [1] is a gate clock (CLK_GOUT_MMC_EMBD_SDCLKIN), so the MMC driver won't be able to change its rate. But that clock actually has CLK_SET_RATE_PARENT flag set in the clock driver [2]. So the right thing to do in this case (and that's basically how it's done in Linux kernel too) is to traverse the clock tree upwards, and try to find the parent capable to do .set_rate (which is usually a divider clock), and use it to change the clock rate. I'm working on exynos_dw_mmc driver [3] right now, making it use CCF clocks, but I can't do that before this patch is applied.
Grepping the U-Boot tree I can see the CLK_SET_RATE_PARENT flag is also used in various IMX clock drivers and STM32MP13 clock driver. I guess without this change those flags will be basically ignored.
Thanks!
[1] https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/exynos850.dt... [2] https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/clk/exynos/clk-ex... [3] https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/mmc/exynos_dw_mmc...
--Sean