Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Jaehoon Chung jh80.chung@samsung.com Cc: Masahiro Yamada yamada.masahiro@socionext.com --- drivers/mmc/matsushita-common.c | 2 ++ drivers/mmc/matsushita-common.h | 1 + 2 files changed, 3 insertions(+)
diff --git a/drivers/mmc/matsushita-common.c b/drivers/mmc/matsushita-common.c index e552a09ea1..33224bb51b 100644 --- a/drivers/mmc/matsushita-common.c +++ b/drivers/mmc/matsushita-common.c @@ -498,6 +498,8 @@ int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, return ret; }
+ matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2, MATSU_SD_INFO2_SCLKDIVEN); + return ret; }
diff --git a/drivers/mmc/matsushita-common.h b/drivers/mmc/matsushita-common.h index 3be91c310e..34631cb43e 100644 --- a/drivers/mmc/matsushita-common.h +++ b/drivers/mmc/matsushita-common.h @@ -38,6 +38,7 @@ #define MATSU_SD_INFO2 0x03c /* IRQ status 2 */ #define MATSU_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ #define MATSU_SD_INFO2_CBSY BIT(14) /* command busy */ +#define MATSU_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */ #define MATSU_SD_INFO2_BWE BIT(9) /* write buffer ready */ #define MATSU_SD_INFO2_BRE BIT(8) /* read buffer ready */ #define MATSU_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */