12 Aug
2003
12 Aug
'03
5:43 p.m.
Dear Chris,
in message 3F38F620.4060207@2net.co.uk you wrote:
The problem occurs in fec_send (in cpu/mpc8xx/fec.c): the BD_ENET_TX_READY bit is set but never cleared, indicating that the packet is ready to send but the hardware is not processing it. The receive side works fine: packets are received and processed as expected. So, I do not suspect the physical path to the outside world. Anybody any ideas what could cause this sort of behaviour? Any known problems with the 852T? What can I look at to find out what is going on? By the way, this is on u-boot 0.4.4.
Check the clock routing for your Tx side. Maybe there is no Tx clock so the bits don't get clocked out?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd@denx.de
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