Hi Remy,
I would like to add CDC support to a davinci (DM365 Soc) board using the musb controller. As the actual driver (musb_udc) does have gadget support, I decided (even if I get some advises that it is a harder way) to port the actual linux driver, changing what I need to provide setup under u-boot.
I made changes to compile the musb as peripheral (as hcd must still be done), and I can compare the debug output with Linux, where everything is fine running on the same HW.
The usb_eth_init does not complete, and a ping request ends with "The remote end did not respond in time". However, a CDC gadget is recognized on both sides (target and PC). On the PC, I get the usb0 interface, and the cdc driver is loaded:
usb 3-2: New USB device found, idVendor=0525, idProduct=a4a1 usb 3-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 usb 3-2: Product: Ethernet Gadget usb 3-2: Manufacturer: Linked-IP DVR365 usb 3-2: configuration #1 chosen from 1 choice usb0: register 'cdc_ether' at usb-0000:01:00.1-2, CDC Ethernet Device, 0a:fa:63:8b:e8:0a
There are some printf I do not understand, and that are not comparable with Linux.
I get a lot of "respond with data transfer before status phase", but as I see in code, it seems to be quite a normal case, and the setup is sent again (is this true ?).
In musb_gadget_queue() entry point (usb_ep_queue from ethernet gadget) there is a check for the parameters, and the ep should be the same as the ep in the request. This is not a case, and an error is reported (see later in error log).
I report the whole log, enabling debug output on both musb driver and ether.c. Do you have some hints to give me to go further ?
Thanks, Stefano
U-Boot 2010.06-00090-g3969a10-dirty (Aug 05 2010 - 12:11:22)
I2C: ready DRAM: 128 MiB Flash: 32 MiB In: serial Out: serial Err: serial Net: Read from EEPROM @ 0x50 failed Ethernet PHY: GENERIC @ 0x00 musb: DaVinci OTG revision 00140901 phy 21f0 control 00 musb: musb_hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn) musb: musb_hdrc: MHDRC RTL version 1.500 musb: musb_hdrc: setup fifo_mode 2 musb: musb_hdrc: 7/9 max ep, 2624/4096 memory musb: musb_hdrc: hw_ep 0shared, max 64 musb: musb_hdrc: hw_ep 1tx, max 512 musb: musb_hdrc: hw_ep 1rx, max 512 musb: musb_hdrc: hw_ep 2tx, max 512 musb: musb_hdrc: hw_ep 2rx, max 512 musb: musb_hdrc: hw_ep 3shared, max 256 musb: musb_hdrc: hw_ep 4shared, max 256 musb: PERIPHERAL mode, status 0, dev98 musb: USB Peripheral mode controller at 01c64000 using PIO, IRQ 0 using musb_hdrc, OUT ep1out IN ep1in STATUS ep2in MAC 8e:28:0f:fa:3c:39 HOST MAC 0a:fa:63:8b:e8:0a musb: <== devctl 98 musb: musb_start: peripheral active -> 1 EMAC, usb0 Hit any key to stop autoboot: 0
Note: setup seems ok, it is the same under Linux.
DVR365 # sete ethact usb0 DVR365 # ping 192.168.90.7 musb: IRQ 00050001 musb: ** IRQ peripheral usb0005 tx0001 rx0000 musb: <== Power=e0, DevCtl=99, int_usb=0x5 musb: BUS RESET as b_idle musb: csr 0011, count 8, myaddr 0, ep0stage idle musb: SetupEnd came in a wrong ep0stage idle musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0100 i0000 l64 musb: musb_hdrc: peripheral reset irq lost! musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=18 musb: TX ep0 fifo 01c64420 count 18 buf 810b51a3 musb: ep0 done request 80f82d98, 18/18 musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0000, count 0, myaddr 0, ep0stage out/status musb: IRQ 00040000 musb: ** IRQ peripheral usb0004 tx0000 rx0000 musb: <== Power=e0, DevCtl=99, int_usb=0x4 musb: BUS RESET as b_peripheral musb: IRQ 00040000 musb: ** IRQ peripheral usb0004 tx0000 rx0000 musb: <== Power=e0, DevCtl=99, int_usb=0x4 musb: BUS RESET as b_peripheral musb: IRQ 00040000 musb: ** IRQ peripheral usb0004 tx0000 rx0000 musb: <== Power=e0, DevCtl=99, int_usb=0x4 musb: BUS RESET as b_peripheral musb: IRQ 00040000 musb: ** IRQ peripheral usb0004 tx0000 rx0000 musb: <== Power=e0, DevCtl=99, int_usb=0x4 musb: BUS RESET as b_peripheral musb: IRQ 00000000 musb: IRQ 00000000
[snip]
musb: IRQ 00000000 musb: IRQ 00000000 musb: IRQ 00000000 musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 0, ep0stage idle musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req00.05 v002b i0000 l0 musb: handled 1, csr 0001, ep0stage in/status musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0000, count 0, myaddr 0, ep0stage in/status musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage idle musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0100 i0000 l18 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=18 musb: TX ep0 fifo 01c64420 count 18 buf 810b51a3 musb: ep0 done request 80f82d98, 18/18 musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0600 i0000 l10 musb: handled 0, csr 0001, ep0stage in eth_setup:... musb: stall (-95) musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0005, count 8, myaddr 43, ep0stage idle musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0600 i0000 l10 musb: handled 0, csr 0001, ep0stage in eth_setup:... musb: stall (-95) musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0005, count 8, myaddr 43, ep0stage idle musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0600 i0000 l10 musb: handled 0, csr 0001, ep0stage in eth_setup:... musb: stall (-95) musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0005, count 8, myaddr 43, ep0stage idle musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0200 i0000 l9 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=9 musb: TX ep0 fifo 01c64420 count 9 buf 810b51a3 musb: ep0 done request 80f82d98, 9/9 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0200 i0000 l80 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=80 musb: TX ep0 fifo 01c64420 count 64 buf 810b51a3 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0000, count 0, myaddr 43, ep0stage in musb: TX ep0 fifo 01c64420 count 16 buf 810b51e3 musb: ep0 done request 80f82d98, 80/80 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0300 i0000 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=4 musb: TX ep0 fifo 01c64420 count 4 buf 810b51a3 musb: ep0 done request 80f82d98, 4/4 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0302 i0409 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=32 musb: TX ep0 fifo 01c64420 count 32 buf 810b51a3 musb: ep0 done request 80f82d98, 32/32 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0301 i0409 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=34 musb: TX ep0 fifo 01c64420 count 34 buf 810b51a3 musb: ep0 done request 80f82d98, 34/34 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req00.09 v0001 i0000 l0 musb: handled 0, csr 0001, ep0stage wait eth_setup:... musb: musb_hdrc periph: enabled ep2in for int IN, maxpacket 16 full speed config #1: 2 mA, Ethernet Gadget, using CDC Ethernet respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=0 musb: ep0 done request 80f82d98, 0/0 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage in/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0307 i0409 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=26 musb: TX ep0 fifo 01c64420 count 26 buf 810b51a3 musb: ep0 done request 80f82d98, 26/26 musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0305 i0409 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=54 musb: TX ep0 fifo 01c64420 count 54 buf 810b51a3 musb: ep0 done request 80f82d98, 54/54 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req01.0b v0001 i0001 l0 musb: handled 0, csr 0001, ep0stage wait eth_setup:... musb: ep1in musb: ep1out musb: musb_hdrc periph: enabled ep1in for bulk IN, maxpacket 64 musb: musb_hdrc periph: enabled ep1out for bulk OUT, maxpacket 64 musb: ep2in musb: musb_hdrc periph: enabled ep2in for int IN, maxpacket 16 musb: Wrong ep in queue: 0 2 status buf queue --> -22
It seems that the parameters passed by eth_setup do not match. ep is always ep0, I missed where is coming the req->ep, as it is saved in the dev structure. Should they always be the same as checked by the musb driver ?
respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=0 musb: ep0 done request 80f82d98, 0/0 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage in/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0303 i0409 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=26 musb: TX ep0 fifo 01c64420 count 26 buf 810b51a3 musb: ep0 done request 80f82d98, 26/26 musb: IRQ 00000000 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0001, count 8, myaddr 43, ep0stage out/status musb: RX ep0 fifo 01c64420 count 8 buf 80f7fd5e musb: SETUP req80.06 v0304 i0409 l255 musb: handled 0, csr 0001, ep0stage in eth_setup:... respond with data transfer before status phase musb: queue to ep0 (OUT/RX), length=28 musb: TX ep0 fifo 01c64420 count 28 buf 810b51a3 musb: ep0 done request 80f82d98, 28/28 musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0000, count 0, myaddr 43, ep0stage out/status musb: IRQ 00000001 musb: ** IRQ peripheral usb0000 tx0001 rx0000 musb: csr 0000, count 0, myaddr 43, ep0stage idle musb: IRQ 00000000