Hi,
Split the patches. And add commit-msg, plz.
Best Regards, Jaehoon Chung
On 7/25/20 9:05 PM, hyyoxhk wrote:
Signed-off-by: hyyoxhk hyyoxhk@163.com
arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos4412-itop-elite.dts | 403 ++++++++++++++ arch/arm/mach-exynos/Kconfig | 4 + board/samsung/itop/Kconfig | 12 + board/samsung/itop/MAINTAINERS | 6 + board/samsung/itop/Makefile | 6 + board/samsung/itop/itop.c | 710 +++++++++++++++++++++++++ board/samsung/itop/setup.h | 389 ++++++++++++++ configs/itop_defconfig | 89 ++++ include/configs/itop.h | 177 ++++++ 10 files changed, 1798 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos4412-itop-elite.dts create mode 100644 board/samsung/itop/Kconfig create mode 100644 board/samsung/itop/MAINTAINERS create mode 100644 board/samsung/itop/Makefile create mode 100644 board/samsung/itop/itop.c create mode 100644 board/samsung/itop/setup.h create mode 100644 configs/itop_defconfig create mode 100644 include/configs/itop.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5726156a2d..bc70d4c58a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ exynos4412-trats2.dtb \
- exynos4412-odroid.dtb
- exynos4412-odroid.dtb \
- exynos4412-itop-elite.dtb
dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb diff --git a/arch/arm/dts/exynos4412-itop-elite.dts b/arch/arm/dts/exynos4412-itop-elite.dts new file mode 100644 index 0000000000..de747ee7b6 --- /dev/null +++ b/arch/arm/dts/exynos4412-itop-elite.dts @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- TOPEET's Exynos4412 based itop board device tree source
- Copyright (C) 2020 hey hyyoxhk@163.com
- */
+/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "exynos4412.dtsi"
+/ {
- model = "TOPEET iTop 4412 Elite board based on Exynos4412";
- compatible = "topeet,itop4412-elite", "samsung,exynos4412";
- aliases {
serial0 = "/serial@13820000";console = "/serial@13820000";mmc0 = &mshc_0;mmc1 = &sdhci2;- };
- chosen {
stdout-path = "serial2:115200n8";- };
- memory@40000000 {
device_type = "memory";reg = <0x40000000 0x40000000>;- };
- serial@13820000 {
status = "okay";- };
- ehci@12580000 {
compatible = "samsung,exynos-ehci";reg = <0x12580000 0x100>;#address-cells = <1>;#size-cells = <1>;/* In order to reset USB ethernet */samsung,vbus-gpio = <&gpc0 1 0>;phy {compatible = "samsung,exynos-usb-phy";reg = <0x125B0000 0x100>;};- };
- emmc-reset {
compatible = "samsung,emmc-reset";reset-gpio = <&gpk0 2 0>;- };
+};
+&i2c_1 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
- s5m8767-pmic@66 {
compatible = "samsung,s5m8767-pmic";reg = <0x66>;wakeup-source;s5m8767,pmic-buck-default-dvs-idx = <3>;s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,<&gpb 6 GPIO_ACTIVE_HIGH>,<&gpb 7 GPIO_ACTIVE_HIGH>;s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,<&gpm3 6 GPIO_ACTIVE_HIGH>,<&gpm3 7 GPIO_ACTIVE_HIGH>;/* VDD_ARM */s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,<1250000>, <1200000>,<1150000>, <1100000>,<1000000>, <950000>;/* VDD_INT */s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,<1100000>, <1100000>,<1000000>, <1000000>,<1000000>, <1000000>;/* VDD_G3D */s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,<1200000>, <1200000>,<1200000>, <1200000>,<1200000>, <1200000>;regulators {ldo1_reg: LDO1 {regulator-name = "VDD_ALIVE";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1100000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};/* SCP uses 1.5v, POP uses 1.2v */ldo2_reg: LDO2 {regulator-name = "VDDQ_M12";regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};ldo3_reg: LDO3 {regulator-name = "VDDIOAP_18";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo4_reg: LDO4 {regulator-name = "VDDQ_PRE";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo5_reg: LDO5 {regulator-name = "VDD_LDO5";op_mode = <0>; /* Always off Mode */};ldo6_reg: LDO6 {regulator-name = "VDD10_MPLL";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1100000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo7_reg: LDO7 {regulator-name = "VDD10_XPLL";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1100000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo8_reg: LDO8 {regulator-name = "VDD10_MIPI";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;op_mode = <1>; /* Normal Mode */};ldo9_reg: LDO9 {regulator-name = "VDD33_LCD";regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3300000>;op_mode = <1>; /* Normal Mode */};ldo10_reg: LDO10 {regulator-name = "VDD18_MIPI";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;op_mode = <1>; /* Normal Mode */};ldo11_reg: LDO11 {regulator-name = "VDD18_ABB1";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo12_reg: LDO12 {regulator-name = "VDD33_UOTG";regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3300000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo13_reg: LDO13 {regulator-name = "VDDIOPERI_18";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo14_reg: LDO14 {regulator-name = "VDD18_ABB02";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo15_reg: LDO15 {regulator-name = "VDD10_USH";regulator-min-microvolt = <1000000>;regulator-max-microvolt = <1000000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo16_reg: LDO16 {regulator-name = "VDD18_HSIC";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo17_reg: LDO17 {regulator-name = "VDDIOAP_MMC012_28";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;op_mode = <1>; /* Normal Mode */};/* Used by HSIC */ldo18_reg: LDO18 {regulator-name = "VDDIOPERI_28";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <3300000>;regulator-always-on;op_mode = <1>; /* Normal Mode */};ldo19_reg: LDO19 {regulator-name = "VDD_LDO19";op_mode = <0>; /* Always off Mode */};ldo20_reg: LDO20 {regulator-name = "VDD28_CAM";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3000000>;op_mode = <1>; /* Normal Mode */};ldo21_reg: LDO21 {regulator-name = "VDD28_AF";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3000000>;op_mode = <1>; /* Normal Mode */};ldo22_reg: LDO22 {regulator-name = "VDDA28_2M";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <3300000>;op_mode = <1>; /* Normal Mode */};ldo23_reg: LDO23 {regulator-name = "VDD28_TF";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;op_mode = <1>; /* Normal Mode */};ldo24_reg: LDO24 {regulator-name = "VDD33_A31";regulator-min-microvolt = <3000000>;regulator-max-microvolt = <3300000>;op_mode = <1>; /* Normal Mode */};ldo25_reg: LDO25 {regulator-name = "VDD18_CAM";regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1800000>;op_mode = <1>; /* Normal Mode */};ldo26_reg: LDO26 {regulator-name = "VDD18_A31";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;op_mode = <1>; /* Normal Mode */};ldo27_reg: LDO27 {regulator-name = "GPS_1V8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;op_mode = <1>; /* Normal Mode */};ldo28_reg: LDO28 {regulator-name = "DVDD12";regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1800000>;op_mode = <1>; /* Normal Mode */};buck1_reg: BUCK1 {regulator-name = "vdd_mif";regulator-min-microvolt = <850000>;regulator-max-microvolt = <1100000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};buck2_reg: BUCK2 {regulator-name = "vdd_arm";regulator-min-microvolt = <850000>;regulator-max-microvolt = <1456250>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};buck3_reg: BUCK3 {regulator-name = "vdd_int";regulator-min-microvolt = <875000>;regulator-max-microvolt = <1200000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};buck4_reg: BUCK4 {regulator-name = "vdd_g3d";regulator-min-microvolt = <750000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};buck5_reg: BUCK5 {regulator-name = "vdd_m12";regulator-min-microvolt = <750000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};buck6_reg: BUCK6 {regulator-name = "vdd12_5m";regulator-min-microvolt = <750000>;regulator-max-microvolt = <1500000>;regulator-always-on;regulator-boot-on;op_mode = <1>; /* Normal Mode */};buck7_reg: BUCK7 {regulator-name = "pvdd_buck7";regulator-min-microvolt = <750000>;regulator-max-microvolt = <2050000>;regulator-boot-on;regulator-always-on;op_mode = <1>; /* Normal Mode */};buck8_reg: BUCK8 {regulator-name = "pvdd_buck8";regulator-min-microvolt = <750000>;regulator-max-microvolt = <1500000>;regulator-boot-on;regulator-always-on;op_mode = <1>; /* Normal Mode */};buck9_reg: BUCK9 {regulator-name = "vddf28_emmc";regulator-min-microvolt = <750000>;regulator-max-microvolt = <3000000>;op_mode = <1>; /* Normal Mode */};};- };
+};
+&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- status = "okay";
+};
+&mshc_0 {
- samsung,bus-width = <8>;
- samsung,timing = <2 1 0>;
- samsung,removable = <0>;
- fifoth_val = <0x203f0040>;
- bus_hz = <400000000>;
- div = <0x3>;
- index = <4>;
- status = "okay";
+}; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 14347e7c7d..a2e1a4a38b 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -73,6 +73,9 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ITOP
- bool "Exynos4412 iTop-4412 board"
endchoice endif
@@ -163,6 +166,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/itop/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/board/samsung/itop/Kconfig b/board/samsung/itop/Kconfig new file mode 100644 index 0000000000..b58ad3fd66 --- /dev/null +++ b/board/samsung/itop/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ITOP
+config SYS_BOARD
- default "itop"
+config SYS_VENDOR
- default "samsung"
+config SYS_CONFIG_NAME
- default "itop"
+endif diff --git a/board/samsung/itop/MAINTAINERS b/board/samsung/itop/MAINTAINERS new file mode 100644 index 0000000000..02356b4f71 --- /dev/null +++ b/board/samsung/itop/MAINTAINERS @@ -0,0 +1,6 @@ +ITOP BOARD +M: hyyoxhk@163.com +S: Maintained +F: board/samsung/itop/ +F: include/configs/itop.h +F: configs/itop_defconfig diff --git a/board/samsung/itop/Makefile b/board/samsung/itop/Makefile new file mode 100644 index 0000000000..509a7cd146 --- /dev/null +++ b/board/samsung/itop/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 hey hyyoxhk@163.com +#
+obj-y := itop.o diff --git a/board/samsung/itop/itop.c b/board/samsung/itop/itop.c new file mode 100644 index 0000000000..2c83ea8a0c --- /dev/null +++ b/board/samsung/itop/itop.c @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 hey hyyoxhk@163.com
- Configuation settings for the iTop-4412 (EXYNOS4412) board.
- */
+#include <common.h> +#include <linux/delay.h> +#include <log.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/arch/cpu.h> +#include <dm.h> +#include <env.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/s5m8767.h> +#include <errno.h> +#include <mmc.h> +#include <usb.h> +#include <usb/dwc2_udc.h> +#include <samsung/misc.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_BOARD_TYPES +/* iTop-4412 board types */ +enum {
- ITOP_TYPE_SCP,
- ITOP_TYPE_POP,
+};
+/* HW revision with core board */ +static unsigned int board_rev = 1;
+u32 get_board_rev(void) +{
- return board_rev;
+}
+/* TODO: gd->board_type*/ +void set_board_type(void) +{
- gd->board_type = ITOP_TYPE_SCP;
+}
+void set_board_revision(void) +{
- /*
* Revision already set by set_board_type() because it can be* executed early.*/+}
+const char *get_board_type(void) +{
- const char *board_type[] = {"SCP", "POP"};
- return board_type[gd->board_type];
+} +#endif
+#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(char *interface, char *devstr) +{
- return env_get("dfu_alt_system");
+}
+char *get_dfu_alt_boot(char *interface, char *devstr) +{
- struct mmc *mmc;
- char *alt_boot;
- int dev_num;
- dev_num = simple_strtoul(devstr, NULL, 10);
- mmc = find_mmc_device(dev_num);
- if (!mmc)
return NULL;- if (mmc_init(mmc))
return NULL;- alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
CONFIG_DFU_ALT_BOOT_EMMC;- return alt_boot;
+} +#endif
+void board_clock_init(void) +{
- unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
- struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
samsung_get_base_clock();+/************************************************************
- Step 1:
- Set PDIV, MDIV, and SDIV values (Refer to (A, M, E, V)
- Change other PLL control values
- ************************************************************/
- /**
* Set dividers for MOUTcore = 1000 MHz** DOUTcore = MOUTcore / (CORE_RATIO +1) = 1000 MHz (0)* ACLK_COREM0 = ARMCLK / (COREM0_RATIO +1) = 250 MHz (3)* ACLK_COREM1 = ARMCLK / (COREM1_RATIO +1) = 125 MHz (7)* PERIPHCLK = DOUTcore / (PERIPH_RATIO + 1) = 1000 MHz (0)* ATCLK = MOUTcore / (ATB_RATIO + 1) = 200 MHz (4)* PCLK_DBG = ATCLK / (PCLK_DBG_RATIO + 1) = 100 MHz (1)* SCLKapll = MOUTapll / (APLL_RATIO + 1) = 500 MHz (1)* ARMCLK = DOUTcore / (CORE2_RATIO + 1) = 1000 MHz (0)*/- /** CLK_DIV_CPU0 */
- clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |APLL_RATIO(7) | CORE2_RATIO(7);- set = CORE_RATIO(0) | COREM0_RATIO(3) | COREM1_RATIO(7) |
PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |APLL_RATIO(1) | CORE2_RATIO(0);- clrsetbits_le32(&clk->div_cpu0, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
continue;- /**
* Set dividers for MOUThpm = 1000 MHz (MOUTapll)** DOUTcopy = MOUThpm / (COPY_RATIO + 1) = 200 MHz (4)* SCLK_HPM = DOUTcopy / (HPM_RATIO + 1) = 200 MHz (0)* ACLK_CORES = ARMCLK / (CORES_RATIO + 1) = 1000 MHz (0)*/- /** CLK_DIV_CPU1 */
- clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
- set = COPY_RATIO(4) | HPM_RATIO(0) | CORES_RATIO(0);
- clrsetbits_le32(&clk->div_cpu1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
continue;- /**
* Set dividers for -->* MOUTdmc = 800 MHz* MOUTdphy = 800 MHz** ACLK_ACP = MOUTdmc / (ACP_RATIO + 1) = 200 MHz (3)* PCLK_ACP = ACLK_ACP / (ACP_PCLK_RATIO + 1) = 100 MHz (1)* SCLK_DPHY = MOUTdphy / (DPHY_RATIO + 1) = 400 MHz (1)* SCLK_DMC = MOUTdmc / (DMC_RATIO + 1) = 400 MHz (1)* ACLK_DMCD = SCLK_DMC / (DMCD_RATIO + 1) = 200 MHz (1)* ACLK_DMCP = ACLK_DMCD / (DMCP_RATIO + 1) = 100 MHz (1)*/- /** CLK_DIV_DMC0 */
- clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);- set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);- clrsetbits_le32(&clk->div_dmc0, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
continue;- /**
* For:* MOUTg2d = 800 MHz* MOUTc2c = 800 Mhz* MOUTpwi = 24 MHz** SCLK_G2D_ACP = MOUTg2d / (G2D_ACP_RATIO + 1) = 200 MHz (3)* SCLK_C2C = MOUTc2c / (C2C_RATIO + 1) = 400 MHz (1)* SCLK_PWI = MOUTpwi / (PWI_RATIO + 1) = 24 MHz (0)* ACLK_C2C = SCLK_C2C / (C2C_ACLK_RATIO + 1) = 200 MHz (1)* DPM_RATIO : It decides frequency of DPM channel clock.*/- /** CLK_DIV_DMC1 */
- clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);- set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(0) |
C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);- clrsetbits_le32(&clk->div_dmc1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
continue;- /**
* MOUTmpll = 800 MHz* MOUTvpll = 54 MHz** ACLK_200 = MOUTACLK_200 / (ACLK_200_RATIO + 1) = 200 MHz (3)* ACLK_100 = MOUTACLK_100 / (ACLK_100_RATIO + 1) = 100 MHz (7)* ACLK_160 = MOUTACLK_160 / (ACLK_160_RATIO + 1) = 160 MHz (4)* ACLK_133 = MOUTACLK_133 / (ACLK_133_RATIO + 1) = 133 MHz (5)* ONENAND = MOUTONENAND_1 / (ONENAND_RATIO + 1) = 160 MHz (0)*/- /** CLK_DIV_TOP */
- clr = ACLK_200_RATIO(7) | ACLK_100_RATIO(15) | ACLK_160_RATIO(7) |
ACLK_133_RATIO(7) | ONENAND_RATIO(7) | ACLK_266_GPS_RATIO(7) |ACLK_400_MCUISP_RATIO(7);- set = ACLK_200_RATIO(3) | ACLK_100_RATIO(7) | ACLK_160_RATIO(4) |
ACLK_133_RATIO(5) | ONENAND_RATIO(0) | ACLK_266_GPS_RATIO(2) |ACLK_400_MCUISP_RATIO(1);- clrsetbits_le32(&clk->div_top, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_top) & DIV_STAT_TOP_CHANGING)
continue;- /**
* ACLK_GDL = MOUTGDL / (GDL_RATIO + 1) = 200 MHz (3)* ACLK_GPL = MOUTGPL / (GPL_RATIO + 1) = 100 MHz (1)*/- /** CLK_DIV_LEFTBUS */
- clr = GDL_RATIO(7) | GPL_RATIO(7);
- set = GDL_RATIO(3) | GPL_RATIO(1);
- clrsetbits_le32(&clk->div_leftbus, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_leftbus) & DIV_STAT_LEFTBUS_CHANGING)
continue;- /**
* ACLK_GDR = MOUTGDR / (GDR_RATIO + 1) = 200 MHz (3)* ACLK_GPR = MOUTGPR / (GPR_RATIO + 1) = 100 MHz (1)*/- /** CLK_DIV_RIGHTBUS */
- clr = GPR_RATIO(7) | GDR_RATIO(7);
- set = GPR_RATIO(3) | GDR_RATIO(1);
- clrsetbits_le32(&clk->div_rightbus, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_rightbus) & DIV_STAT_RIGHTBUS_CHANGING)
continue;- /**
* MOUTUART[1-4] = 800 Mhz (MPLL)** SCLK_UART0 = MOUTUART0 / (UART0_RATIO + 1) = 100 MHz (7)* SCLK_UART1 = MOUTUART1 / (UART1_RATIO + 1) = 100 MHz (7)* SCLK_UART2 = MOUTUART2 / (UART2_RATIO + 1) = 100 MHz (7)* SCLK_UART3 = MOUTUART3 / (UART3_RATIO + 1) = 100 MHz (7)* SCLK_UART4 = MOUTUART4 / (UART4_RATIO + 1) = 100 MHz (7)*/- /** CLK_DIV_PERIL0 */
- clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
UART3_RATIO(15) | UART4_RATIO(15);- set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
UART3_RATIO(7) | UART4_RATIO(7);- clrsetbits_le32(&clk->div_peril0, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
continue;- /**
* For MOUTMMC0-3 = 800 MHz (MPLL)** SCLK_MIPIHSI = MOUTMIPIHSI / (MIPIHSI_RATIO + 1) = 200 MHz (3)*/- /* CLK_DIV_FSYS0 */
- clr = MIPIHSI_RATIO(15);
- set = MIPIHSI_RATIO(3);
- clrsetbits_le32(&clk->div_fsys0, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys0) & DIV_STAT_FSYS0_CHANGING)
continue;- /**
* For MOUTMMC0-3 = 800 MHz (MPLL)** DOUTMMC0 = MOUTMMC0 / (MMC0_RATIO + 1) = 100 MHz (7)* SCLK_MMC0 = DOUTMMC0 / (MMC0_PRE_RATIO + 1) = 50 MHz (1)* DOUTMMC1 = MOUTMMC1 / (MMC1_RATIO + 1) = 100 MHz (7)* SCLK_MMC1 = DOUTMMC1 / (MMC1_PRE_RATIO + 1) = 50 MHz (1)*/- /* CLK_DIV_FSYS1 */
- clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
MMC1_PRE_RATIO(255);- set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
MMC1_PRE_RATIO(1);- clrsetbits_le32(&clk->div_fsys1, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
continue;- /**
* For MOUTmmc0-3 = 800 MHz (MPLL)** DOUTmmc3 = MOUTmmc3 / (MMC2_RATIO + 1) = 100 MHz (7)* sclk_mmc3 = DOUTmmc3 / (MMC2_PRE_RATIO + 1) = 50 MHz (1)* DOUTmmc2 = MOUTmmc2 / (MMC3_RATIO + 1) = 100 MHz (7)* sclk_mmc2 = DOUTmmc2 / (MMC3_PRE_RATIO + 1) = 50 MHz (1)*/- /* CLK_DIV_FSYS2 */
- clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
MMC3_PRE_RATIO(255);- set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
MMC3_PRE_RATIO(1);- clrsetbits_le32(&clk->div_fsys2, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
continue;- /**
* For MOUTmmc4 = 800 MHz (MPLL)** DOUTmmc4 = MOUTmmc4 / (MMC4_RATIO + 1) = 100 MHz (7)* sclk_mmc4 = DOUTmmc4 / (MMC4_PRE_RATIO + 1) = 100 MHz (0)*/- /* CLK_DIV_FSYS3 */
- clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
- set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
- clrsetbits_le32(&clk->div_fsys3, clr, set);
- /* Wait for divider ready status */
- while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
continue;+/************************************************************
- Step 2:
- Set K, AFC, MRR, MFR values if necessary
- (Refer to (A, M, E, V)PLL_CON1 SFRs)
- Turn on a PLL (Refer to (A, M, E, V) PLL_CON0 SFRs)
- ************************************************************/
- /* Set APLL to 1000MHz */
- /** APLL_CON1 */
- clr = AFC(31) | LOCK_CON_DLY(31) | LOCK_CON_IN(3) |
LOCK_CON_OUT(3) | FEED_EN(1) | AFC_ENB(1) |DCC_ENB(1) | BYPASS(1) | RESV0(1) | RESV1(1);- set = AFC(0) | LOCK_CON_DLY(8) | LOCK_CON_IN(3) |
LOCK_CON_OUT(0) | FEED_EN(0) | AFC_ENB(0) |DCC_ENB(1) | BYPASS(0) | RESV0(0) | RESV1(0);- clrsetbits_le32(&clk->apll_con1, clr, set);
- /** APLL_CON0 */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(0) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
- /* Wait for PLL to be locked */
- while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
continue;- /* Set MPLL to 800MHz */
- /** MPLL_CON1 */
- clr = AFC(31) | LOCK_CON_DLY(31) | LOCK_CON_IN(3) |
LOCK_CON_OUT(3) | FEED_EN(1) | AFC_ENB(1) |DCC_ENB(1) | BYPASS(1) | RESV0(1) | RESV1(1);- set = AFC(0) | LOCK_CON_DLY(8) | LOCK_CON_IN(3) |
LOCK_CON_OUT(0) | FEED_EN(0) | AFC_ENB(0) |DCC_ENB(1) | BYPASS(0) | RESV0(0) | RESV1(0);- clrsetbits_le32(&clk->mpll_con1, clr, set);
- /** MPLL_CON0 */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
- /* Wait for PLL to be locked */
- while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
continue;- /* Set EPLL to 192MHz */
- /** EPLL_CON2 */
- clr = ICP_BOOST(7) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(1) | EV_AFC_ENB(1) | EV_DCC_ENB(1) | EXTAFC(1);- set = ICP_BOOST(0) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(0) | EV_AFC_ENB(0) | EV_DCC_ENB(1) | EXTAFC(0);- clrsetbits_le32(&clk->epll_con2, clr, set);
- /** EPLL_CON1 */
- /* there is null */
- /** EPLL_CON0 */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(2) | PDIV(2) | MDIV(64) | FSEL(0) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->epll_con0, clr_pll_con0, set);
- /* Wait for PLL to be locked */
- while (!(readl(&clk->epll_con0) & PLL_LOCKED_BIT))
continue;- /* Set VPLL to 54MHz */
- /** VPLL_CON2 */
- clr = ICP_BOOST(7) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(1) | EV_AFC_ENB(1) | EV_DCC_ENB(1) | EXTAFC(1);- set = ICP_BOOST(0) | EV_FSEL(1) | FVCO_EN(1) | EV_BYPASS(1) |
SSCG_EN(0) | EV_AFC_ENB(0) | EV_DCC_ENB(1) | EXTAFC(0);- clrsetbits_le32(&clk->vpll_con2, clr, set);
- /** VPLL_CON1 */
- /* there is null */
- /** VPLL_CON0 */
- clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
PLL_ENABLE(1);- set = SDIV(3) | PDIV(3) | MDIV(54) | FSEL(0) | PLL_ENABLE(1);
- clrsetbits_le32(&clk->vpll_con0, clr_pll_con0, set);
- /* Wait for PLL to be locked */
- while (!(readl(&clk->vpll_con0) & PLL_LOCKED_BIT))
continue;+/************************************************************
- *Step 3:
- Wait until the PLL is locked
- ************************************************************/
- clr = PLL_LOCKTIME(65535);
- /** APLL LOCKTIME 1000MHz */
- set = PLL_LOCKTIME(PDIV(3) * 270);
- clrsetbits_le32(&clk->apll_lock, clr, set);
- /** MPLL LOCKTIME 800MHz */
- set = PLL_LOCKTIME(PDIV(3) * 270);
- clrsetbits_le32(&clk->mpll_lock, clr, set);
- /** EPLL LOCKTIME 192MHz */
- set = PLL_LOCKTIME(PDIV(2) * 270);
- clrsetbits_le32(&clk->epll_lock, clr, set);
- /** VPLL LOCKTIME 54MHz */
- set = PLL_LOCKTIME(PDIV(3) * 270);
- clrsetbits_le32(&clk->vpll_lock, clr, set);
+/************************************************************
- Step 4:
- Select the PLL output clock instead of input reference clock,
- after PLL output clock is stabilized.
- (Refer to CLK_SRC_CPU SFR for APLL and MPLL,
- CLK_SRC_TOP0 for EPLL and VPLL)
- Once a PLL is turned on, do not turn it off.
- ************************************************************/
- /**
* before set system clocks,we switch system clocks src to FINpll** Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; MOUTAPLLFOUT* MUX_CORE_SEL: MOUTAPLL ; SCLKMPLL* MUX_HPM_SEL: MOUTAPLL ; SCLKMPLL* MUX_MPLL_USER_SEL_C: FINPLL ; FOUTMPLL*/- /** CLK_SRC_CPU */
- clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);- set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
MUX_MPLL_USER_SEL_C(1);- clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
- /* Wait for mux change */
- while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
continue;- /**
* Set CMU_DMC default clocks src to APLL** Bit values: 0 ; 1* MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL* MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL* MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL* MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT* MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)* MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL* MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL* MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1*/- /** CLK_SRC_DMC */
- clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);- set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
MUX_MPLL_SEL(1) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(0) |MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);- clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
- /* Wait for mux change */
- while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
continue;- /**
* Set CMU_TOP default clocks src to APLL** Bit values: 0 ; 1* MUX_ONENAND_1_SEL MOUTONENAND ; SCLKVPLL* MUX_EPLL_SEL FINPLL ; FOUTEPLL* MUX_VPLL_SEL FINPLL ; FOUTEPLL* MUX_ACLK_200_SEL SCLKMPLL ; SCLKAPLL* MUX_ACLK_100_SEL SCLKMPLL ; SCLKAPLL* MUX_ACLK_160_SEL SCLKMPLL ; SCLKAPLL* MUX_ACLK_133_SEL SCLKMPLL ; SCLKAPLL* MUX_ONENAND_SEL ACLK_133 ; ACLK_160*/- /* CLK_SRC_TOP0 */
- clr = MUX_ONENAND_1_SEL(1) | MUX_EPLL_SEL(1) | MUX_VPLL_SEL(1) |
MUX_ACLK_200_SEL(1) | MUX_ACLK_100_SEL(1) | MUX_ACLK_160_SEL(1) |MUX_ACLK_133_SEL(1) | MUX_ONENAND_SEL(1);- set = MUX_ONENAND_1_SEL(0) | MUX_EPLL_SEL(1) | MUX_VPLL_SEL(1) |
MUX_ACLK_200_SEL(0) | MUX_ACLK_100_SEL(0) | MUX_ACLK_160_SEL(0) |MUX_ACLK_133_SEL(0) | MUX_ONENAND_SEL(1);- clrsetbits_le32(&clk->src_top0, clr, set);
- /* Wait for mux change */
- while (readl(&clk->mux_stat_top0) & MUX_STAT_TOP0_CHANGING)
continue;- /**
* Bit values: 0 ; 1* MUX_ACLK_266_GPS_SEL SCLKMPLL_USER_T ; SCLKAPLL* MUX_ACLK_400_MCUISP_SEL SCLKMPLL_USER_T ; SCLKAPLL* MUX_MPLL_USER_SEL_T FINPLL ; SCLKMPLLL* MUX_ACLK_266_GPS_SUB_SEL FINPLL ; DIVOUT_ACLK_266_GPS* MUX_ACLK_200_SUB_SEL FINPLL ; DIVOUT_ACLK_200* MUX_ACLK_400_MCUISP_SUB_SEL FINPLL*/- /* CLK_SRC_TOP1 */
- clr = MUX_ACLK_266_GPS_SEL(1) | MUX_ACLK_400_MCUISP_SEL(1) |
MUX_MPLL_USER_SEL_T(1) | MUX_ACLK_266_GPS_SUB_SEL(1) |MUX_ACLK_200_SUB_SEL(1) | MUX_ACLK_400_MCUISP_SUB_SEL(1);- set = MUX_ACLK_266_GPS_SEL(0) | MUX_ACLK_400_MCUISP_SEL(0) |
MUX_MPLL_USER_SEL_T(1) | MUX_ACLK_266_GPS_SUB_SEL(1) |MUX_ACLK_200_SUB_SEL(1) | MUX_ACLK_400_MCUISP_SUB_SEL(1);- clrsetbits_le32(&clk->src_top1, clr, set);
- /* Wait for mux change */
- while (readl(&clk->mux_stat_top1) & MUX_STAT_TOP1_CHANGING)
continue;- /* CLK_SRC_LEFTBUS */
- clr = MUX_GDL_SEL(1) | MUX_MPLL_USER_SEL_L(1);
- set = MUX_GDL_SEL(0) | MUX_MPLL_USER_SEL_L(1);
- clrsetbits_le32(&clk->src_leftbus, clr, set);
- /* Wait for mux change */
- while (readl(&clk->mux_stat_leftbus) & MUX_STAT_LEFTBUS_CHANGING)
continue;- /* CLK_SRC_RIGHTBUS */
- clr = MUX_GDR_SEL(1) | MUX_MPLL_USER_SEL_R(1);
- set = MUX_GDR_SEL(0) | MUX_MPLL_USER_SEL_R(1);
- clrsetbits_le32(&clk->src_rightbus, clr, set);
- /* Wait for mux change */
- while (readl(&clk->mux_stat_rightbus) & MUX_STAT_RIGHTBUS_CHANGING)
continue;- /** CLK_SRC_PERIL0 */
- clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
UART3_SEL(15) | UART4_SEL(15);- set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) |
UART3_SEL(6) | UART4_SEL(6);- clrsetbits_le32(&clk->src_peril0, clr, set);
- /** CLK_SRC_FSYS */
- clr = MMC1_SEL(15) | MMC2_SEL(15) | MMC3_SEL(15) |
MMC4_SEL(15) | MIPIHSI_SEL(1);- set = MMC1_SEL(6) | MMC2_SEL(6) | MMC3_SEL(6) |
MMC4_SEL(6) | MIPIHSI_SEL(0);- clrsetbits_le32(&clk->src_fsys, clr, set);
+}
+static void board_gpio_init(void) +{
- /* eMMC Reset Pin */
- gpio_request(EXYNOS4X12_GPIO_K02, "eMMC Reset");
- gpio_direction_output(EXYNOS4X12_GPIO_K02, 1);
- /* LED */
- gpio_request(EXYNOS4X12_GPIO_L20, "LED2");
- gpio_direction_output(EXYNOS4X12_GPIO_L20, 1);
+#ifdef CONFIG_CMD_USB
- /* USB3503A Reference Intn */
- gpio_request(EXYNOS4X12_GPIO_M23, "USB3503A Intn");
- gpio_direction_output(EXYNOS4X12_GPIO_M23, 0);
- /* USB3503A Connect */
- gpio_request(EXYNOS4X12_GPIO_M33, "USB3503A Connect");
- gpio_direction_output(EXYNOS4X12_GPIO_M33, 0);
- /* USB3503A Reset */
- gpio_request(EXYNOS4X12_GPIO_M24, "USB3503A Reset");
- gpio_direction_output(EXYNOS4X12_GPIO_M24, 0);
- /* Reset */
- gpio_direction_output(EXYNOS4X12_GPIO_M24, 1);
- /* From usb3503 linux driver ? */
- mdelay(4);
- /* Connect */
- gpio_direction_output(EXYNOS4X12_GPIO_M33, 1);
+#endif +}
+int exynos_early_init_f(void) +{
- board_clock_init();
- return 0;
+}
+int exynos_init(void) +{
- board_gpio_init();
- return 0;
+}
+int exynos_power_init(void) +{
- int ret;
- struct udevice *dev;
- ret = pmic_get("s5m8767-pmic", &dev);
- /* TODO(sjg@chromium.org): Use driver model to access clock */
- if (!ret)
s5m8767_enable_32khz_cp(dev);- if (ret == -ENODEV)
return 0;- ret = regulators_enable_boot_on(false);
- if (ret)
return ret;- return 0;
+}
+#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{
- return 0;
+}
+struct dwc2_plat_otg_data s5pc210_otg_data = {
- .phy_control = s5pc210_phy_control,
- .regs_phy = EXYNOS4X12_USBPHY_BASE,
- .regs_otg = EXYNOS4X12_USBOTG_BASE,
- .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
- .usb_flags = PHY0_SLEEP,
+}; +#endif
+#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
+int board_usb_init(int index, enum usb_init_type init) +{
- debug("USB_udc_probe\n");
- return dwc2_udc_probe(&s5pc210_otg_data);
+} +#endif diff --git a/board/samsung/itop/setup.h b/board/samsung/itop/setup.h new file mode 100644 index 0000000000..ff96eb9219 --- /dev/null +++ b/board/samsung/itop/setup.h @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2020 hey hyyoxhk@163.com
- */
+#ifndef _SETUP_H +#define _SETUP_H
+#include <config.h> +#include <asm/arch/cpu.h>
+/* this state is changing for register */ +#define MUX_STAT_CHANGING 0x100 +#define DIV_STAT_CHANGING 0x1
+/* A/M/EV PLL_CON0 */ +#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* A/M PLL_CON1 */ +#define AFC(x) ((x) & 0x1f) +#define LOCK_CON_DLY(x) (((x) & 0x1f) << 8) +#define LOCK_CON_IN(x) (((x) & 0x3) << 12) +#define LOCK_CON_OUT(x) (((x) & 0x3) << 14) +#define FEED_EN(x) (((x) & 0x1) << 16) +#define AFC_ENB(x) (((x) & 0x1) << 20) +#define DCC_ENB(x) (((x) & 0x1) << 21) +#define BYPASS(x) (((x) & 0x1) << 22) +#define RESV0(x) (((x) & 0x1) << 23) +#define RESV1(x) (((x) & 0x1) << 24)
+/* E/V PLL_CON1 */ +#define K(x) ((x) & 0xffff) +#define MFR(x) (((x) & 0xff) << 16) +#define MRR(x) (((x) & 0x1f) << 24) +#define SEL_PF(x) (((x) & 0x3) << 29)
+/* E/V PLL_CON2 */ +#define ICP_BOOST(x) ((x) & 0x3) +#define EV_FSEL(x) (((x) & 0x1) << 2) +#define FVCO_EN(x) (((x) & 0x1) << 3) +#define EV_BYPASS(x) (((x) & 0x1) << 4) +#define SSCG_EN(x) (((x) & 0x1) << 5) +#define EV_AFC_ENB(x) (((x) & 0x1) << 6) +#define EV_DCC_ENB(x) (((x) & 0x1) << 7) +#define EXTAFC(x) (((x) & 0x1f) << 8)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) +#define MUX_HPM_SEL(x) (((x) & 0x1) << 20) +#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define HPM_SEL(x) (((x) & 0x7) << 20) +#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24) +#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
CORE_SEL(MUX_STAT_CHANGING) | \HPM_SEL(MUX_STAT_CHANGING) | \MPLL_USER_SEL_C(MUX_STAT_CHANGING))+/* A/M/E/V PLL_LOCK */ +#define PLL_LOCKTIME(x) ((x) & 0xffff)
+/* CLK_DIV_CPU0 */ +#define CORE_RATIO(x) ((x) & 0x7) +#define COREM0_RATIO(x) (((x) & 0x7) << 4) +#define COREM1_RATIO(x) (((x) & 0x7) << 8) +#define PERIPH_RATIO(x) (((x) & 0x7) << 12) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define CORE2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_CPU1 */ +#define COPY_RATIO(x) ((x) & 0x7) +#define HPM_RATIO(x) (((x) & 0x7) << 4) +#define CORES_RATIO(x) (((x) & 0x7) << 8)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CORE(x) ((x) & 0x1) +#define DIV_COREM0(x) (((x) & 0x1) << 4) +#define DIV_COREM1(x) (((x) & 0x1) << 8) +#define DIV_PERIPH(x) (((x) & 0x1) << 12) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_CORE2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
DIV_COREM0(DIV_STAT_CHANGING) | \DIV_COREM1(DIV_STAT_CHANGING) | \DIV_PERIPH(DIV_STAT_CHANGING) | \DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_CORE2(DIV_STAT_CHANGING))+/* CLK_DIV_STAT_CPU1 */ +#define DIV_COPY(x) ((x) & 0x1) +#define DIV_HPM(x) (((x) & 0x1) << 4) +#define DIV_CORES(x) (((x) & 0x1) << 8)
+#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
DIV_HPM(DIV_STAT_CHANGING) | \DIV_CORES(DIV_STAT_CHANGING))+/* CLK_SRC_DMC */ +#define MUX_C2C_SEL(x) ((x) & 0x1) +#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4) +#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8) +#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12) +#define MUX_PWI_SEL(x) (((x) & 0xf) << 16) +#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20) +#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24) +#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
+/* CLK_MUX_STAT_DMC */ +#define C2C_SEL(x) ((x) & 0x7) +#define DMC_BUS_SEL(x) (((x) & 0x7) << 4) +#define DPHY_SEL(x) (((x) & 0x7) << 8) +#define MPLL_SEL(x) (((x) & 0x7) << 12) +#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20) +#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24) +#define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
+#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
DMC_BUS_SEL(MUX_STAT_CHANGING) | \DPHY_SEL(MUX_STAT_CHANGING) | \MPLL_SEL(MUX_STAT_CHANGING) |\G2D_ACP0_SEL(MUX_STAT_CHANGING) | \G2D_ACP1_SEL(MUX_STAT_CHANGING) | \G2D_ACP_SEL(MUX_STAT_CHANGING))+/* CLK_DIV_DMC0 */ +#define ACP_RATIO(x) ((x) & 0x7) +#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4) +#define DPHY_RATIO(x) (((x) & 0x7) << 8) +#define DMC_RATIO(x) (((x) & 0x7) << 12) +#define DMCD_RATIO(x) (((x) & 0x7) << 16) +#define DMCP_RATIO(x) (((x) & 0x7) << 20)
+/* CLK_DIV_DMC1 */ +#define G2D_ACP_RATIO(x) ((x) & 0xf) +#define C2C_RATIO(x) (((x) & 0x7) << 4) +#define PWI_RATIO(x) (((x) & 0xf) << 8) +#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12) +#define DVSEM_RATIO(x) (((x) & 0x7f) << 16) +#define DPM_RATIO(x) (((x) & 0x7f) << 24)
+/* CLK_DIV_STAT_DMC0 */ +#define DIV_ACP(x) ((x) & 0x1) +#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4) +#define DIV_DPHY(x) (((x) & 0x1) << 8) +#define DIV_DMC(x) (((x) & 0x1) << 12) +#define DIV_DMCD(x) (((x) & 0x1) << 16) +#define DIV_DMCP(x) (((x) & 0x1) << 20)
+#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
DIV_ACP_PCLK(DIV_STAT_CHANGING) | \DIV_DPHY(DIV_STAT_CHANGING) | \DIV_DMC(DIV_STAT_CHANGING) | \DIV_DMCD(DIV_STAT_CHANGING) | \DIV_DMCP(DIV_STAT_CHANGING))+/* CLK_DIV_STAT_DMC1 */ +#define DIV_G2D_ACP(x) ((x) & 0x1) +#define DIV_C2C(x) (((x) & 0x1) << 4) +#define DIV_PWI(x) (((x) & 0x1) << 8) +#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12) +#define DIV_DVSEM(x) (((x) & 0x1) << 16) +#define DIV_DPM(x) (((x) & 0x1) << 24)
+#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
DIV_C2C(DIV_STAT_CHANGING) | \DIV_PWI(DIV_STAT_CHANGING) | \DIV_C2C_ACLK(DIV_STAT_CHANGING) | \DIV_DVSEM(DIV_STAT_CHANGING) | \DIV_DPM(DIV_STAT_CHANGING))+/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_1_SEL(x) ((x) & 0x1) +#define MUX_EPLL_SEL(x) (((x) & 0x1) << 4) +#define MUX_VPLL_SEL(x) (((x) & 0x1) << 8) +#define MUX_ACLK_200_SEL(x) (((x) & 0x1) << 12) +#define MUX_ACLK_100_SEL(x) (((x) & 0x1) << 16) +#define MUX_ACLK_160_SEL(x) (((x) & 0x1) << 20) +#define MUX_ACLK_133_SEL(x) (((x) & 0x1) << 24) +#define MUX_ONENAND_SEL(x) (((x) & 0x1) << 28)
+/* CLK_MUX_STAT_TOP */ +#define ONENAND_1_SEL(x) ((x) & 0x3) +#define EPLL_SEL(x) (((x) & 0x3) << 4) +#define VPLL_SEL(x) (((x) & 0x3) << 8) +#define ACLK_200_SEL(x) (((x) & 0x3) << 12) +#define ACLK_100_SEL(x) (((x) & 0x3) << 16) +#define ACLK_160_SEL(x) (((x) & 0x3) << 20) +#define ACLK_133_SEL(x) (((x) & 0x3) << 24) +#define ONENAND_SEL(x) (((x) & 0x3) << 28)
+#define MUX_STAT_TOP0_CHANGING (ONENAND_1_SEL(MUX_STAT_CHANGING) | \
EPLL_SEL(MUX_STAT_CHANGING) | \EPLL_SEL(MUX_STAT_CHANGING) | \VPLL_SEL(MUX_STAT_CHANGING) | \ACLK_200_SEL(MUX_STAT_CHANGING) | \ACLK_100_SEL(MUX_STAT_CHANGING) | \ACLK_160_SEL(MUX_STAT_CHANGING) | \ACLK_133_SEL(MUX_STAT_CHANGING) | \ONENAND_SEL(MUX_STAT_CHANGING))+/* CLK_SRC_TOP1 */ +#define MUX_ACLK_266_GPS_SEL(x) (((x) & 0x1) << 4) +#define MUX_ACLK_400_MCUISP_SEL(x) (((x) & 0x1) << 8) +#define MUX_MPLL_USER_SEL_T(x) (((x) & 0x1) << 12) +#define MUX_ACLK_266_GPS_SUB_SEL(x) (((x) & 0x1) << 16) +#define MUX_ACLK_200_SUB_SEL(x) (((x) & 0x1) << 20) +#define MUX_ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x1) << 24)
+/* CLK_MUX_STAT_TOP1 */ +#define ACLK_266_GPS_SEL(x) (((x) & 0x3) << 4) +#define ACLK_400_MCUISP_SEL(x) (((x) & 0x3) << 8) +#define MPLL_USER_SEL_T(x) (((x) & 0x3) << 12) +#define ACLK_266_GPS_SUB_SEL(x) (((x) & 0x3) << 16) +#define ACLK_200_SUB_SEL(x) (((x) & 0x3) << 20) +#define ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x3) << 24)
+#define MUX_STAT_TOP1_CHANGING (MUX_ACLK_266_GPS_SEL(MUX_STAT_CHANGING) | \
ACLK_400_MCUISP_SEL(MUX_STAT_CHANGING) | \MPLL_USER_SEL_T(MUX_STAT_CHANGING) | \ACLK_266_GPS_SUB_SEL(MUX_STAT_CHANGING) | \ACLK_200_SUB_SEL(MUX_STAT_CHANGING) | \ACLK_400_MCUISP_SUB_SEL(MUX_STAT_CHANGING))+/* CLK_DIV_TOP */ +#define ACLK_200_RATIO(x) ((x) & 0x7) +#define ACLK_100_RATIO(x) (((x) & 0xf) << 4) +#define ACLK_160_RATIO(x) (((x) & 0x7) << 8) +#define ACLK_133_RATIO(x) (((x) & 0x7) << 12) +#define ONENAND_RATIO(x) (((x) & 0x7) << 16) +#define ACLK_266_GPS_RATIO(x) (((x) & 0x7) << 20) +#define ACLK_400_MCUISP_RATIO(x) (((x) & 0x7) << 24)
+#define DIV_STAT_TOP_CHANGING (ACLK_400_MCUISP_RATIO(DIV_STAT_CHANGING) | \
ACLK_266_GPS_RATIO(DIV_STAT_CHANGING) | \ONENAND_RATIO(DIV_STAT_CHANGING) | \ACLK_133_RATIO(DIV_STAT_CHANGING) | \ACLK_160_RATIO(DIV_STAT_CHANGING) | \ACLK_100_RATIO(DIV_STAT_CHANGING) | \ACLK_200_RATIO(DIV_STAT_CHANGING))+/* CLK_SRC_LEFTBUS */ +#define MUX_GDL_SEL(x) ((x) & 0x1) +#define MUX_MPLL_USER_SEL_L(x) (((x) & 0x1) << 4)
+/* CLK_MUX_STAT_LEFTBUS */ +#define GDL_SEL(x) ((x) & 0x7) +#define MPLL_USER_SEL_L(x) (((x) & 0x7) << 4)
+#define MUX_STAT_LEFTBUS_CHANGING (GDL_SEL(MUX_STAT_CHANGING) | \
MPLL_USER_SEL_L(MUX_STAT_CHANGING))+/* CLK_DIV_LEFTBUS */ +#define GDL_RATIO(x) ((x) & 0x7) +#define GPL_RATIO(x) (((x) & 0x7) << 4)
+/* CLK_DIV_STAT_LEFTBUS */ +#define DIV_GDL(x) ((x) & 0x1) +#define DIV_GPL(x) (((x) & 0x1) << 4)
+#define DIV_STAT_LEFTBUS_CHANGING (DIV_GDL(DIV_STAT_CHANGING) | \
DIV_GPL(DIV_STAT_CHANGING))+/* CLK_SRC_RIGHTBUS */ +#define MUX_GDR_SEL(x) ((x) & 0x1) +#define MUX_MPLL_USER_SEL_R(x) (((x) & 0x1) << 4)
+/* CLK_MUX_STAT_RIGHTBUS */ +#define GDR_SEL(x) ((x) & 0x7) +#define MPLL_USER_SEL_R(x) (((x) & 0x7) << 4)
+#define MUX_STAT_RIGHTBUS_CHANGING (GDR_SEL(MUX_STAT_CHANGING) | \
MPLL_USER_SEL_R(MUX_STAT_CHANGING))+/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO(x) ((x) & 0x7) +#define GDR_RATIO(x) (((x) & 0x7) << 4)
+/* CLK_DIV_STAT_RIGHTBUS */ +#define DIV_GDR(x) ((x) & 0x1) +#define DIV_GPR(x) ((x) & 0x1)
+#define DIV_STAT_RIGHTBUS_CHANGING (DIV_GDR(DIV_STAT_CHANGING) | \
DIV_GPR(DIV_STAT_CHANGING))+/* CLK_SRC_PERIL0 */ +#define UART0_SEL(x) ((x) & 0xf) +#define UART1_SEL(x) (((x) & 0xf) << 4) +#define UART2_SEL(x) (((x) & 0xf) << 8) +#define UART3_SEL(x) (((x) & 0xf) << 12) +#define UART4_SEL(x) (((x) & 0xf) << 16)
+/* CLK_DIV_PERIL0 */ +#define UART0_RATIO(x) ((x) & 0xf) +#define UART1_RATIO(x) (((x) & 0xf) << 4) +#define UART2_RATIO(x) (((x) & 0xf) << 8) +#define UART3_RATIO(x) (((x) & 0xf) << 12) +#define UART4_RATIO(x) (((x) & 0xf) << 16)
+/* CLK_DIV_STAT_PERIL0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MMC1_SEL(x) (((x) & 0xf) << 4) +#define MMC2_SEL(x) (((x) & 0xf) << 8) +#define MMC3_SEL(x) (((x) & 0xf) << 12) +#define MMC4_SEL(x) (((x) & 0xf) << 16) +#define MIPIHSI_SEL(x) (((x) & 0x1) << 24)
+/* CLK_DIV_FSYS0 */ +#define MIPIHSI_RATIO(x) (((x) & 0xf) << 20)
+/* CLK_DIV_STAT_FSYS0 */ +#define DIV_MIPIHSI(x) (((x) & 0x1) << 20)
+#define DIV_STAT_FSYS0_CHANGING (DIV_MIPIHSI(DIV_STAT_CHANGING))
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0xf) +#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8) +#define MMC1_RATIO(x) (((x) & 0xf) << 16) +#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
+/* CLK_DIV_STAT_FSYS1 */ +#define DIV_MMC0(x) ((x) & 1) +#define DIV_MMC0_PRE(x) (((x) & 1) << 8) +#define DIV_MMC1(x) (((x) & 1) << 16) +#define DIV_MMC1_PRE(x) (((x) & 1) << 24)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC0_PRE(DIV_STAT_CHANGING) | \DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC1_PRE(DIV_STAT_CHANGING))+/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO(x) ((x) & 0xf) +#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8) +#define MMC3_RATIO(x) (((x) & 0xf) << 16) +#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
+/* CLK_DIV_STAT_FSYS2 */ +#define DIV_MMC2(x) ((x) & 0x1) +#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8) +#define DIV_MMC3(x) (((x) & 0x1) << 16) +#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
+#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
DIV_MMC2_PRE(DIV_STAT_CHANGING) | \DIV_MMC3(DIV_STAT_CHANGING) | \DIV_MMC3_PRE(DIV_STAT_CHANGING))+/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO(x) ((x) & 0x7) +#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
+/* CLK_DIV_STAT_FSYS3 */ +#define DIV_MMC4(x) ((x) & 0x1) +#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
+#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
DIV_MMC4_PRE(DIV_STAT_CHANGING))+#endif diff --git a/configs/itop_defconfig b/configs/itop_defconfig new file mode 100644 index 0000000000..74521a6c8d --- /dev/null +++ b/configs/itop_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_EXYNOS=y +CONFIG_SYS_TEXT_BASE=0x43e00000 +CONFIG_ARCH_EXYNOS4=y +CONFIG_TARGET_ITOP=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_IDENT_STRING=" for iTop-4412" +CONFIG_DEFAULT_DEVICE_TREE="exynos4412-itop-elite" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +# CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_TYPES=y +CONFIG_SYS_PROMPT="u-boot # " +CONFIG_CMD_ADTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_RANDOM is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_EXT4=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_ENV_EXT4_INTERFACE="mmc" +CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_VIRT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x40000000 +CONFIG_FASTBOOT_BUF_SIZE=0x02000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SYS_I2C_S3C24X0=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_S5P=y +# CONFIG_SPI_FLASH is not set +CONFIG_DM_ETH=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_S5M8767=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_TEE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Samsung" +CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6601 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_HOST_ETHER=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MIPI_DSI=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_LIB_HW_RAND=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/itop.h b/include/configs/itop.h new file mode 100644 index 0000000000..3235e44e90 --- /dev/null +++ b/include/configs/itop.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2020 hey hyyoxhk@163.com
- Configuation settings for the iTop-4412 (EXYNOS4412) board.
- */
+#ifndef __CONFIG_ITOP_H +#define __CONFIG_ITOP_H
+#include <configs/exynos4-common.h>
+#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif
+#define CONFIG_MACH_TYPE 5115
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +/* Reserve the last 1 MiB for the secure firmware */ +#define CONFIG_SYS_MEM_TOP_HIDE BIT(20) +#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE
+/* memtest works on */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+#include <linux/sizes.h>
+/* select serial console configuration */
+/* Console configuration */
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
- GENERATED_GBL_DATA_SIZE)+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_OVERWRITE
+/* Partitions name */ +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform"
+#define CONFIG_DFU_ALT \
- "uImage fat 0 1;" \
- "zImage fat 0 1;" \
- "exynos4412-itop-elite.dtb fat 0 1;" \
- ""PARTS_BOOT" part 0 1;" \
- ""PARTS_ROOT" part 0 2\0" \
+#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K)
+#define CONFIG_DFU_ALT_BOOT_EMMC \
- "u-boot raw 0x3e 0x800 mmcpart 1;" \
- "bl1 raw 0x0 0x1e mmcpart 1;" \
- "bl2 raw 0x1e 0x1d mmcpart 1;" \
- "tzsw raw 0x83e 0x138 mmcpart 1\0"
+#define CONFIG_DFU_ALT_BOOT_SD \
- "u-boot raw 0x3f 0x800;" \
- "bl1 raw 0x1 0x1e;" \
- "bl2 raw 0x1f 0x1d;" \
- "tzsw raw 0x83f 0x138\0"
+#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 1) \
- func(MMC, mmc, 0)
+#include <config_distro_bootcmd.h>
+/*
- Bootable media layout:
- dev: SD eMMC(part boot)
- BL1 1 0
- BL2 31 30
- UBOOT 63 62
- TZSW 2111 2110
- ENV 2560 2560(part user)
- MBR Primary partiions:
- Num Name Size Offset
- BOOT: 100MiB 2MiB
- ROOT: -
- */
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \
"boot.scr\0" \- "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \
"${kernelname}\0" \- "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${ramdisk_addr_r} " \
"${initrdname}\0" \- "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdt_addr_r} " \
"${fdtfile}\0" \- "check_ramdisk=" \
"if run loadinitrd; then " \"setenv initrd_addr ${ramdisk_addr_r};" \"else " \"setenv initrd_addr -;" \"fi;\0" \- "check_dtb=" \
"if run loaddtb; then " \"setenv fdt_addr ${fdt_addr_r};" \"else " \"setenv fdt_addr;" \"fi;\0" \- "kernel_args=" \
"setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \" rootwait ${console} ${opts}\0" \- "boot_script=" \
"run loadbootscript;" \"source ${scriptaddr}\0" \- "boot_fit=" \
"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kernel_addr_r}#${board_name}\0" \- "boot_uimg=" \
"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \- "boot_zimg=" \
"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \- "autoboot=" \
"if test -e mmc ${mmcbootdev} boot.scr; then; " \"run boot_script; " \"elif test -e mmc ${mmcbootdev} Image.itb; then; " \"run boot_fit;" \"elif test -e mmc ${mmcbootdev} zImage; then; " \"run boot_zimg;" \"elif test -e mmc ${mmcbootdev} uImage; then; " \"run boot_uimg;" \"fi;\0" \- "console=" CONFIG_DEFAULT_CONSOLE \
- "mmcbootdev=0\0" \
- "mmcbootpart=1\0" \
- "mmcrootdev=0\0" \
- "mmcrootpart=2\0" \
- "dfu_alt_system="CONFIG_DFU_ALT \
- "dfu_alt_info=Please reset the board\0" \
- "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
- "consoleoff=set console console=ram; save; reset\0" \
- "initrdname=uInitrd\0" \
- "ramdisk_addr_r=0x42000000\0" \
- "scriptaddr=0x42000000\0" \
- "fdt_addr_r=0x41900000\0" \
- "kernel_addr_r=0x41e00000\0" \
- BOOTENV
+/* GPT */
+/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA
+/* USB */ +#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_MISC_COMMON
+#define CONFIG_EXYNOS_FB
+#endif /* __CONFIG_H */