This series update SiFive Unleashed clock driver and Cadence MACB driver so that: 1. It is in sync with upstream Linux driver 2. It uses latest DT bindings as-per upstream Linux driver
With this series, we can now use latest DT bindings with U-Boot. I have tested SiFive Serial driver and Cadence MACB ethernet driver with this changes and both work fine.
The legacy FSBL will still pass DTB with older DT bindings which will break the updated SiFive Unleashed clock driver. To tackle this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive Unleashed so that OpenSBI will override and pass updated DTB to U-Boot.
The updated DTB passed by OpenSBI is in fact the DTB build by upstream Linux so we can straight away pass this DTB to Linux as well.
This series can be found in riscv_unleashed_clk_sync_v6 branch at: https://github.com/avpatel/u-boot.git
To try this series use latest OpenSBI at: https://github.com/riscv/opensbi.git And Linux-5.2-rc1 from v5.2-rc1_unleashed branch at: https://github.com/avpatel/linux.git
Changes since v5: - Addressed Ramon's comments in PATCH6 - Addressed Bin's comments in PATCH7
Changes since v4: - Rebased patches upon Ramon's MACB changes (Refer, https://patchwork.ozlabs.org/patch/1114025/) - Added PATCH7 to setup ethaddr based on board serial number read from OTP - Added PATCH8 to update documentation
Changes since v3: - Extend MACB ethernet driver for SiFive Unleashed board (just like Linux)
Changes since v2: - Dropped PATCH6 which adds new compatible string to MACB driver because more changes are required in MACB driver for different ethernet speeds
Changes since v1: - Dropped GEMGXL clock driver - Added new compatible string for SiFive MACB ethernet
Anup Patel (8): clk: sifive: Factor-out PLL library as separate module clk: sifive: Sync-up WRPLL library with upstream Linux clk: sifive: Sync-up DT bindings header with upstream Linux clk: sifive: Sync-up main driver with upstream Linux clk: sifive: Drop GEMGXL clock driver net: macb: Extend MACB driver for SiFive Unleashed board riscv: sifive: fu540: Setup ethaddr env variable using OTP doc: sifive-fu540: Update README for steps to create FW_PAYLOAD
board/sifive/fu540/Kconfig | 1 - board/sifive/fu540/fu540.c | 122 ++++++ configs/sifive_fu540_defconfig | 1 + doc/README.sifive-fu540 | 356 ++++++++---------- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/analogbits/Kconfig | 4 + drivers/clk/analogbits/Makefile | 3 + .../{sifive => analogbits}/wrpll-cln28hpc.c | 168 ++++----- drivers/clk/sifive/Kconfig | 10 - drivers/clk/sifive/Makefile | 4 - drivers/clk/sifive/fu540-prci.c | 123 +++--- drivers/clk/sifive/gemgxl-mgmt.c | 60 --- drivers/net/macb.c | 86 ++++- include/dt-bindings/clk/sifive-fu540-prci.h | 29 -- include/dt-bindings/clock/sifive-fu540-prci.h | 18 + .../linux/clk}/analogbits-wrpll-cln28hpc.h | 70 ++-- 17 files changed, 551 insertions(+), 506 deletions(-) create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%) delete mode 100644 drivers/clk/sifive/gemgxl-mgmt.c delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%)
-- 2.17.1