Hi Bin
Hi Rick,
On Thu, Oct 31, 2019 at 11:10 AM Rick Chen rickchen36@gmail.com wrote:
Hi Bin
Hi Rick,
On Fri, Oct 25, 2019 at 2:18 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang.
Signed-off-by: Rick Chen rick@andestech.com Cc: KC Lin kclin@andestech.com Cc: Alan Kao alankao@andestech.com
arch/riscv/cpu/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 0a2ce6d..ee6d471 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -174,7 +174,7 @@ spl_clear_bss: spl_clear_bss_loop: SREG zero, 0(t0) addi t0, t0, REGBYTES
bne t0, t1, spl_clear_bss_loop
blt t0, t1, spl_clear_bss_loopThis leaves bss section not completely zeroed.
I don't think this will clear bss section incompletely. Can you check it again ? Or explain more details why you think so ?
Sorry I meant to say the other way around. This incorrectly clear the last a few bytes that are less than REGBYTES to zero.
OK . I will also modify as ALIGN(8) in ld to avoid this boundary exceeding.
Thanks Rick
Regards, Bin