HS400 speed mode is now supported in J7200 SoC[1]. Therefore add mmc-hs400-1_8v tag in sdhci0 device tree node.
Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021)
[2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf, (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)
Signed-off-by: Aswath Govindraju a-govindraju@ti.com --- arch/arm/dts/k3-j7200-main.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index 11314640750d..ae4f7896ef4b 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -428,10 +428,14 @@ ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x0>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; ti,strobe-sel = <0x77>; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; bus-width = <8>; + mmc-hs400-1_8v; mmc-hs200-1_8v; mmc-ddr-1_8v; dma-coherent; @@ -451,7 +455,12 @@ ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; dma-coherent; };