From: Hugo Villeneuve hvilleneuve@dimonoff.com
With DM enabled, there is no need for board code to initialize the FEC interface.
The ethernet PHYs on the symphony carrier board have a dedicated crystal/oscillator. If the SOM has the EC configuration option (onboard ethernet PHY), it also has a dedicated crystal/oscillator. So in all cases, there is no need to enable the RGMII TX clk output.
This follows a similar change introduced by Fabio Estevam: Link: https://lore.kernel.org/u-boot/20231019170441.1610453-1-festevam@gmail.com/
Signed-off-by: Hugo Villeneuve hvilleneuve@dimonoff.com --- board/variscite/imx8mn_var_som/imx8mn_var_som.c | 13 ------------- 1 file changed, 13 deletions(-)
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 61b9455a8f4..994fd4f7058 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -12,7 +12,6 @@ #include <fdt_support.h> #include <i2c_eeprom.h> #include <malloc.h> -#include <asm/io.h> #include <asm/global_data.h> #include <dt-bindings/gpio/gpio.h> #include <linux/libfdt.h> @@ -46,20 +45,8 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed;
-static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -} - int board_init(void) { - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - return 0; }
base-commit: 4655b75335384e040358a2e3e478cc42f32a96c9