Hi Mike,
don't you think this is a little bit to shortsighted? There are many other parameters beyond the CPU clock that could be modified in such a way. We have some code in the PMC440 board code that sets up the PCI sync clock dynamically dependant on a GPIO (M66EN pci pin). So I would vote for a more generic configuration than by a CPU frequency parameter. Just think about this: should 667 MHz on an EPx always mean 166 MHz PLB clock? 667MHZ with 133MHz PLB might also be a typical configuration (e.g. when you need 66MHz EBC clock ....).
So what about a function that takes the complete strapping values as parameters (I think 4 longs) instead of nothing but the CPU frequency.
Matthias
On Wednesday 20 February 2008 17:54:20 Mike Nuss wrote:
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after startup to change the speed of the clocks. This patch adds the option CFG_PLL_RECONFIG. If this option is set to 667, the CPU initialization code will reconfigure the PLL to run the system with a CPU frequency of 667MHz and PLB frequency of 166MHz, without the need for an external EEPROM.
Signed-off-by: Mike Nuss mike@terascala.com Cc: Stefan Roese sr@denx.de