All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8 except the DM646x. This was decided by the design team driving the design. This patch updates the CLE and ALE values for DM646x. Updated patches for DM646x will be sent shortly. This applies to u-boot-nand-flash git
Signed-off-by: Sandeep Paulraj s-paulraj@ti.com --- include/asm-arm/arch-davinci/nand_defs.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index b49e3af..a77c4c8 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -28,8 +28,13 @@
#include <asm/arch/hardware.h>
+#ifdef CONFIG_SOC_DM646x +#define MASK_CLE 0x80000 +#define MASK_ALE 0x40000 +#else #define MASK_CLE 0x10 #define MASK_ALE 0x08 +#endif
#define NAND_CE0CLE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x10)) #define NAND_CE0ALE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x0a))