
27 Jun
2015
27 Jun
'15
7:11 p.m.
Hi Peng,
On Thu, Jun 11, 2015 at 7:30 AM, Peng Fan Peng.Fan@freescale.com wrote:
- Add DDR script for mx6qpsabreauto board.
- On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz.
- On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log: U-Boot 2015.07-rc2-00034-gba46bb1 (Jun 11 2015 - 16:46:41 +0800)
CPU: Freescale i.MX6Q rev2.0 996 MHz (running at 792 MHz)
Please make it to display i.MX6QP instead.
Regards,
Fabio Estevam