From: Haiying Wang Haiying.Wang@freescale.com
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 10 ++++++++- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 8 ++++-- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 31 +++++++++++++++++++++++++---- 3 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 3fec100..8fdafdb 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1176,7 +1176,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj) + unsigned int dbw_cap_adj, + unsigned int size_only) { unsigned int i; unsigned int cas_latency; @@ -1394,6 +1395,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, printf("CS%d is disabled.\n", i); }
+ /* + * In the case we only need to compute the ddr sdram size, we only need + * to set csn registers, so return from here. + */ + if (size_only) + return 0; + set_ddr_eor(ddr, popts);
#if !defined(CONFIG_FSL_DDR1) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 98acb8d..8c24131 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -55,7 +55,8 @@ typedef struct { #define STEP_ALL 0xFFF
extern unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step); +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only);
extern const char * step_to_string(unsigned int step);
@@ -64,7 +65,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, - unsigned int dbw_capacity_adjust); + unsigned int dbw_capacity_adjust, + unsigned int size_only); extern unsigned int compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 6d582e9..b89b471 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, }
unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only) { unsigned int i, j; unsigned int all_controllers_memctl_interleaving = 0; @@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) &pinfo->memctl_opts[i], &ddr_reg[i], &timing_params[i], pinfo->dimm_params[i], - dbw_capacity_adjust[i]); + dbw_capacity_adjust[i], + size_only); }
default: @@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void) memset(&info, 0, sizeof(fsl_ddr_info_t));
/* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD); + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
/* Check for memory controller interleaving. */ memctl_interleaved = 0; @@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void) info.memctl_opts[i].memctl_interleaving = 0; debug("Recomputing with memctl_interleaving off.\n"); total_memory = fsl_ddr_compute(&info, - STEP_ASSIGN_ADDRESSES); + STEP_ASSIGN_ADDRESSES, + 0); } }
@@ -477,3 +480,21 @@ phys_size_t fsl_ddr_sdram(void)
return total_memory; } + +/* + * fsl_ddr_sdram_size() - This function only returns the size of the total + * memory without setting ddr control registers. + */ +phys_size_t +fsl_ddr_sdram_size(void) +{ + fsl_ddr_info_t info; + unsigned long long total_memory = 0; + + memset(&info, 0 , sizeof(fsl_ddr_info_t)); + + /* Compute it once normally. */ + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); + + return total_memory; +}