[U-Boot] [PATCH 08/10] MIPS: mips32/cache.S: save return address in t9 register

Synchronize the code with mips64/cache.S, in order to allow further unifications.

Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com --- arch/mips/cpu/mips32/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 8158ea8..6d31909 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -34,7 +34,7 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif

-#define RA t8 +#define RA t9

/* * 16kB is the maximum size of instruction and data caches on MIPS 4K,