The code from Xilinx is as follows...
void XIo_Out32(XIo_Address OutAddress, Xuint32 Value) { __asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "r" (OutAddress)); }
This code is broken. The "r" operand specification sais "a register operand is allowed provided that it is in a general register." Of course R0 is a GPR as well. I think you need to use "m" (any kind of address that the machine supports in general) here:
__asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "m" (OutAddress));If you want to avoid using R0, you should be able to use the "clobber" list. like this: __asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "r" (OutAddress) : "r0" );
Jocke
It appears that PPC has yet another register operand, "b". "b" appears to mean all "r" registers but r0. The asm would then become: __asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "b" (OutAddress));
Anyone that knows more about the "b" operand?