On 08/21/2012 05:37 AM, Josh Wu wrote:
Hi, Andreas
On 8/17/2012 5:24 PM, Andreas Bießmann wrote:
can you please add some README entry describing these new config parameters? Namely CONFIG_ATMEL_NAND_HW_PMECC, CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE (can't this be derived from some already available NAND information?) and CONFIG_PMECC_INDEX_TABLE_OFFSET.
OK, I will add a README file to explain all the parameters. this CONFIG_PMECC_SECTOR_SIZE means how many bytes to generate out PMECC code. It only can be 512 and 1024. So for a nand chip whose page size is 2048, if CONFIG_PMECC_SECTOR_SIZE is set as 512, then PMECC will generate PMECC code for each 512 bytes.
I think it cannot be derived from nand information.
So this is basically nand->ecc.size? While this can't be directly read from the chip, usually there's a convention for a given type of NAND chip on a given controller. Do you really need to support both 512 and 1024 for any single chip?
Why do you set nand->ecc.size to mtd->writesize if that isn't the actual ECC chunk size?
-Scott