On Wed, Mar 11, 2015 at 05:12:12PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@freescale.com
Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller.
No, this is wrong. They do not. CMA remaps pages to be non-cacheable rather than the old technique where the above statement was true.
There's some corner cases which make that less effective than it once was, and as I've already said, those need to be fixed. The reason that these were missed is because all the ARM CMA work bypassed me - CMA on ARM has had zero review from the point of view of the ARM architecture, so it's not surprising it gets stuff like this wrong.
Once that's fixed, setting bit 22 is not necessary.